公开(公告)号：US20220416024A1

公开(公告)日：2022-12-29

申请号：US17903914

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Dax CRUM ,  Patrick KEYS ,  Tahir GHANI ,  Susmita GHOSE ,  Ted COOK, JR.

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/027 ,  H01L27/092 ,  H01L21/683 ,  H01L21/8238

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.