公开(公告)号：US20230387324A1

公开(公告)日：2023-11-30

申请号：US18228139

申请日：2023-07-31

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Tahir GHANI ,  Susmita GHOSE ,  Zachary GEIGER

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

公开(公告)号：US20220406895A1

公开(公告)日：2022-12-22

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20190334034A1

公开(公告)日：2019-10-31

申请号：US16509421

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Michael JACKSON ,  Anand MURTHY ,  Glenn GLASS ,  Saurabh MORARKA ,  Chandra MOHAPATRA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US20230074199A1

公开(公告)日：2023-03-09

申请号：US17986715

申请日：2022-11-14

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Dax M. CRUM ,  Sean MA ,  Tahir GHANI ,  Susmita GHOSE ,  Stephen CEA ,  Rishabh MEHANDRU

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

公开(公告)号：US20200006492A1

公开(公告)日：2020-01-02

申请号：US16022510

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20240145549A1

公开(公告)日：2024-05-02

申请号：US18409509

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/165 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20220416024A1

公开(公告)日：2022-12-29

申请号：US17903914

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Dax CRUM ,  Patrick KEYS ,  Tahir GHANI ,  Susmita GHOSE ,  Ted COOK, JR.

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/027 ,  H01L27/092 ,  H01L21/683 ,  H01L21/8238

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20170062569A1

公开(公告)日：2017-03-02

申请号：US15119119

申请日：2014-06-13

Applicant: Intel Corporation

Inventor： Kimin JUN ,  Willy RACHMADY ,  Glenn GLASS ,  Anand MURTHY

IPC: H01L29/161 ,  H01L21/02 ,  H01L25/065 ,  H01L23/528 ,  H01L23/29 ,  H01L25/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L29/161 ,  H01L21/02532 ,  H01L21/2007 ,  H01L21/56 ,  H01L21/76251 ,  H01L23/298 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657 ,  H01L25/50

Abstract: Techniques are disclosed for wafer bonding with an encapsulation layer. A first semiconductor substrate is provided. An encapsulation layer is then formed on top of the first semiconductor substrate. The encapsulation layer is formed of an encapsulation material that creates a stable oxide when exposed to an oxidizing agent. A first bonding layer is formed on top of the encapsulation layer. Next, a second semiconductor substrate is provided. A second bonding layer is formed on top of the second bonding layer. Thereafter, the first semiconductor substrate is bonded to the second semiconductor substrate by attaching the first bonding layer to the second bonding layer.

Abstract translation: 公开了用于与封装层的晶片接合的技术。 提供第一半导体衬底。 然后在第一半导体衬底的顶部上形成封装层。 封装层由暴露于氧化剂时产生稳定氧化物的封装材料形成。 在封装层的顶部形成第一结合层。 接下来，提供第二半导体衬底。 第二接合层形成在第二接合层的顶部。 此后，通过将第一接合层附接到第二接合层，将第一半导体衬底接合到第二半导体衬底。