公开(公告)号：US20170365677A1

公开(公告)日：2017-12-21

申请号：US15673219

申请日：2017-08-09

Applicant: Intel Corporation

Inventor： Uday SHAH ,  Brian S. DOYLE ,  Justin K. BRASK ,  Robert S. CHAU ,  Thomas A. LETSON

IPC: H01L29/423 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.