公开(公告)号：US20200227477A1

公开(公告)日：2020-07-16

申请号：US16631156

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20170271576A1

公开(公告)日：2017-09-21

申请号：US15503680

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3295 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20160291641A1

公开(公告)日：2016-10-06

申请号：US15037639

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Brian S. DOYLE ,  Han Wui THEN ,  Valluri RAO ,  Niloy MUKHERJEE ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC: G06F1/16 ,  H04M1/02 ,  H05K3/30 ,  H05K1/02 ,  H05K3/46

CPC classification number: G06F1/1652 ,  G06F1/1626 ,  G06F1/1643 ,  G06F1/1656 ,  G06F2203/04102 ,  G06F2203/04103 ,  G09F9/00 ,  G09G3/2092 ,  G09G2300/0426 ,  G09G2380/02 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1266 ,  H04M1/0268 ,  H05K1/028 ,  H05K1/0296 ,  H05K3/30 ,  H05K3/4682

Abstract: A flexible electronic computing device is described. In one embodiment, a flexible display is formed on a flexible substrate. A plurality of electronic components are attached to the flexible substrate. A plurality of conductive signal lines are formed on the flexible substrate, the signal lines electrically coupling the electronic components to the flexible display.

Abstract translation: 描述了一种灵活的电子计算设备。 在一个实施例中，柔性显示器形成在柔性基板上。 多个电子部件附接到柔性基板。 多个导电信号线形成在柔性基板上，信号线将电子部件电耦合到柔性显示器。

公开(公告)号：US20220199801A1

公开(公告)日：2022-06-23

申请号：US17132996

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Brian S. DOYLE ,  Urusa ALAAN ,  Van H. LE ,  Elijah V. KARPOV ,  Kaan OGUZ ,  Arnab SEN GUPTA

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/683 ,  H01L29/78

Abstract: Embodiments disclosed herein include a semiconductor devices with back end of line (BEOL) transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a BEOL stack over the semiconductor substrate. In an embodiment, a field effect transistor (FET) is embedded in the BEOL stack. In an embodiment, the FET comprises a channel, a gate dielectric over the channel, where the gate dielectric is single crystalline, a gate electrode over the gate dielectric, and a source electrode and a drain electrode passing through the gate dielectric to contact the channel.

公开(公告)号：US20220199609A1

公开(公告)日：2022-06-23

申请号：US17133595

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Urusa ALAAN ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Benjamin ORR ,  Nicholas THOMSON ,  Ayan KAR ,  Arnab SEN GUPTA ,  Kaan OGUZ ,  Brian S. DOYLE ,  Prashant MAJHI ,  Van H. LE ,  Elijah V. KARPOV

IPC: H01L27/02 ,  H02H9/04

Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

公开(公告)号：US20220181335A1

公开(公告)日：2022-06-09

申请号：US17673670

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

公开(公告)号：US20200243543A1

公开(公告)日：2020-07-30

申请号：US16635966

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Elijah V. KARPOV ,  Brian S. DOYLE

IPC: H01L27/108 ,  G11C11/4096

Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.

公开(公告)号：US20170011912A1

公开(公告)日：2017-01-12

申请号：US15119683

申请日：2014-03-18

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Valluri R. RAO ,  Robert S. CHAU

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/02513 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02422 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02675 ,  H01L21/763 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料和布置在柔性衬底和多晶半导体材料之间和之后的多晶电介质。 多晶半导体材料。 多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20150072490A1

公开(公告)日：2015-03-12

申请号：US14534088

申请日：2014-11-05

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Roza KOTLYAR ,  Uday SHAH ,  Charles C. KUO

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract translation: 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：US20140239345A1

公开(公告)日：2014-08-28

申请号：US14268938

申请日：2014-05-02

Applicant: INTEL CORPORATION

Inventor： Boyan BOYANOV ,  Anand S. MURTHY ,  Brian S. DOYLE ,  Robert S. CHAU

IPC: H01L29/78 ,  H01L27/092

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract translation: 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。