公开(公告)号：US20240402442A1

公开(公告)日：2024-12-05

申请号：US18326458

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaoqian Li ,  Kaveh Hosseini ,  Tim T. Hoang

IPC: G02B6/42

Abstract: The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A portion of the FAU extends into the substrate cutout. A stress relief mechanism can secure the fiber optic cable attached to the FAU to the substrate to at least partially isolate the FAU-PIC attachment from external mechanical forces applied to the optical fiber cable. The integrated circuit component can be attached to a socket that comprises a socket cutout into which an FAU can extend.

公开(公告)号：US20250004206A1

公开(公告)日：2025-01-02

申请号：US18343175

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Tim T. Hoang ,  Kaveh Hosseini ,  Omkar G. Karhade

IPC: G02B6/30 ,  G02B6/42

Abstract: In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.

公开(公告)号：US20230411369A1

公开(公告)日：2023-12-21

申请号：US17841451

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Kaveh Hosseini ,  Chia-Pin Chiu ,  Tim T. Hoang ,  Tolga Acikalin ,  Cooper S. Levy

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/167 ,  G02B6/4274 ,  H01L23/5381 ,  H01L2224/16225 ,  H01L23/49811 ,  H01L24/16 ,  H01L23/5383

Abstract: In one embodiment, an integrated circuit package includes a package substrate with a cavity, an integrated circuit device, a bridge, a photonic integrated circuit (PIC), and an electronic integrated circuit (EIC). The integrated circuit device is electrically coupled to the package substrate. The bridge and the PIC are in the cavity of the package substrate, and the bridge is electrically coupled to the package substrate. The EIC is above, and electrically coupled to, the bridge and the PIC.

公开(公告)号：US20230341622A1

公开(公告)日：2023-10-26

申请号：US17725090

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Omkar G. Karhade ,  Kaveh Hosseini ,  Tim T. Hoang ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/42

CPC classification number: G02B6/1225 ,  G02B6/428 ,  G02B6/4266 ,  G02B2006/12061

Abstract: Covered cavity structure for Photonic integrated circuits (PICs) that include a micro-ring resonator (MRR) with a heater. Air cavities are etched or otherwise thinned into an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. Variations in size, shape, and location of the covered air cavity associated with an MRR provide customizable options for thermal management. A thin film across an upper surface covers the air cavity, providing a barrier to underfill in the air cavity and preventing interference of underfill with performance of silicon waveguides. When arrayed into a plurality of MRRs, the thin film can cover the plurality of MRRs.