公开(公告)号：US20220068802A1

公开(公告)日：2022-03-03

申请号：US17133080

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Gokul MALYAVANATHAM ,  Philip YASHAR ,  Mark KOEPER ,  Bharath BANGALORE RAJEEVA ,  Krishna T. MARLA ,  Umang DESAI ,  Harry B. RUSSELL

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, a second conductive interconnect line in a second ILD layer above the first ILD layer, and a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer. In another example, a method of fabricating an integrated circuit structure includes forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer, etching a hanging via that lands on the etch stop layer, and performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.