公开(公告)号：US20220157735A1

公开(公告)日：2022-05-19

申请号：US17586672

申请日：2022-01-27

Applicant: Intel Corporation

Inventor： Flavio GRIGGIO ,  Philip YASHAR ,  Anthony V. MULE ,  Gopinath TRICHY ,  Gokul MALYAVANATHAM

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

公开(公告)号：US20220068802A1

公开(公告)日：2022-03-03

申请号：US17133080

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Gokul MALYAVANATHAM ,  Philip YASHAR ,  Mark KOEPER ,  Bharath BANGALORE RAJEEVA ,  Krishna T. MARLA ,  Umang DESAI ,  Harry B. RUSSELL

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, a second conductive interconnect line in a second ILD layer above the first ILD layer, and a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer. In another example, a method of fabricating an integrated circuit structure includes forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer, etching a hanging via that lands on the etch stop layer, and performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.

公开(公告)号：US20180327887A1

公开(公告)日：2018-11-15

申请号：US15777502

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Christopher J. WIEGAND ,  Philip YASHAR ,  Anurag CHAUDHRY

IPC: C22C27/04 ,  C23C14/34 ,  C23C14/56 ,  H01J37/34 ,  C22C1/04

CPC classification number: C22C27/04 ,  C22C1/045 ,  C23C14/3414 ,  C23C14/564 ,  H01J37/3405 ,  H01J37/3426

Abstract: Refractory metal alloy targets for reducing particles in physical vapor deposition processing and refractory metal-based layer for integrated circuit applications (for example, crystallization barrier layers in non-volatile memory devices) are disclosed herein. An exemplary method for reducing particles in a PVD chamber include positioning a refractory metal alloy target in the PVD chamber, positioning a substrate in the PVD chamber a distance from the refractory metal alloy target, and sputtering material from the refractory metal alloy target to form a refractory metal-based layer over the substrate. The refractory metal alloy target includes a refractory metal (for example, tungsten or molybdenum) alloyed with a body-centered cubic (BCC) metal (for example, niobium, tantalum, vanadium, or a combination thereof). The BCC metal has a Young's modulus lower than a Young's modulus of the refractory metal.