公开(公告)号：US20210319098A1

公开(公告)日：2021-10-14

申请号：US17254235

申请日：2019-04-23

Applicant: INTEL CORPORATION

Inventor： OLEG POGORELIK ,  ALEX NAYSHTUT ,  OMER BEN-SHALOM ,  DENIS KLIMOV ,  RAIZY KELLERMANN ,  GUY BARNHART-MAGEN ,  VADIM SUKHOMLINOV

IPC: G06F21/55 ,  G06N20/00 ,  G06N5/04

Abstract: Techniques and apparatuses to harden AI systems against various attacks are provided. Among the different techniques and apparatuses, is provided, techniques and apparatuses that expand the domain for an inference model to include both visible classes and well as hidden classes. The hidden classes can be used to detect possible probing attacks against the model.

公开(公告)号：US20190042746A1

公开(公告)日：2019-02-07

申请号：US16021411

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Alex Nayshtut ,  VADIM SUKHOMLINOV ,  KOICHI YAMADA ,  AJAY HARIKUMAR ,  VENKAT GOKULRANGAN

IPC: G06F21/56 ,  G06F21/55

Abstract: The disclosed embodiments generally relate to detecting malware through detection of micro-architectural changes (morphing events) when executing a code at a hardware level (e.g., CPU). An exemplary embodiment relates to a computer system having: a memory circuitry comprising an executable code; a central processing unit (CPU) in communication with the memory circuitry and configured to execute the code; a performance monitoring unit (PMU) associated with the CPU, the PMU configured to detect and count one or more morphing events associated with execution of the code and to determine if the counted number of morphine events exceed a threshold value; and a co-processor configured to initiate a memory scan of the memory circuitry to identify a malware in the code.

公开(公告)号：US20190243768A1

公开(公告)日：2019-08-08

申请号：US15891028

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： KSHITIJ DOSHI ,  ROMAN DEMENTIEV ,  VADIM SUKHOMLINOV

IPC: G06F12/0875 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3834 ,  G06F2212/452

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a destination memory address information. An execution unit is coupled with the decode unit. The execution unit, in response to the decode of the instruction, is to store memory addresses, for at least all initial writes to corresponding data items, which are to occur after the instruction in original program order, to a memory address log. A start of the memory address log is to correspond to the destination memory address information. Other processors, methods, systems, and instructions are also disclosed.

公开(公告)号：US20190004851A1

公开(公告)日：2019-01-03

申请号：US15637476

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： KSHITIJ A. DOSHI ,  VADIM SUKHOMLINOV ,  ROMAN DEMENTIEV

IPC: G06F9/46 ,  G06F12/0831 ,  G06F9/30

Abstract: A method to perform atomic transactions in non-volatile memory (NVM) under hardware transactional memory is disclosed. The method includes tracking an order among transaction log entries that includes arranging transaction logs in an order that is based on when corresponding transactions were executed. Moreover, the method includes, using the ordered transaction logs to recover data states of the nonvolatile memory, by identifying a first unconfirmed transaction associated with a transaction completion uncertainty event based on a corresponding one of the transaction logs including a first commit marker but not including a confirm marker, undoing first ones of the transactions in reverse time order starting at a last transaction that recorded a second commit marker, up to and including the first unconfirmed transaction that recorded the first commit marker, and redoing second ones of the transactions in forward time order from a first confirmed transaction up to but not including the first unconfirmed transaction that recorded the first commit marker.