公开(公告)号：US20230291567A1

公开(公告)日：2023-09-14

申请号：US17692930

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： VIDHYA KRISHNAN ,  SIDDHARTHA CHHABRA ,  VEDVYAS SHANBHOGUE ,  XIAOYU RUAN ,  ADITYA NAVALE ,  JULIEN CARRENO

IPC: H04L9/32 ,  H04L9/08 ,  G06F12/14 ,  G06T1/60

CPC classification number: H04L9/3242 ,  H04L9/0877 ,  G06F12/1408 ,  G06T1/60

Abstract: Described herein is a paging technique that can be implemented in any accelerator with attached memory and support for operating on encrypted data when the CPU is not within the trusted compute base (TCB). Memory storing data that is encrypted using hardware physical address (HPA)-based encrypted can be paged out of accelerator device memory by decoupling encryption from the hardware physical address and re-encrypting the data for page-out. Upon page-in, the data is decrypted, the integrity and authenticity of the data is verified, then the data is re-encrypted using HPA-based encryption.

公开(公告)号：US20200082059A1

公开(公告)日：2020-03-12

申请号：US16126060

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  VIDHYA KRISHNAN ,  SANDEEP SODHI ,  SREEKANTH MAVILA ,  ALTUG KOKER ,  ADITYA NAVALE ,  SCOTT JANUS ,  Changliang WANG

IPC: G06F21/12 ,  G06T15/00 ,  H04N21/254 ,  G06F9/48 ,  G06F21/60 ,  H04L9/08

Abstract: Apparatus and method for scalable content protection. For example, one embodiment of an apparatus comprises: cryptographic management circuitry to securely store one or more keys associated with one or more media apps/applications; a plurality of processing engines, each processing engine comprising circuitry to process media content of the one or more media apps/applications; and a scheduler to schedule processing of the media content by the processing engines; wherein the cryptographic management circuitry is to restore a first cryptographic state including a first key associated with a first media app/application and/or first media content responsive to a request to process the first media content on a first processing engine.

公开(公告)号：US20200310973A1

公开(公告)日：2020-10-01

申请号：US16366266

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ALTUG KOKER ,  VIDHYA KRISHNAN ,  RONALD W. SILVAS ,  JOHN H. FEIT ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  ABHISHEK R. APPU

IPC: G06F12/0837 ,  G06F9/38 ,  H04L9/06 ,  G06F16/907

Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

公开(公告)号：US20170347065A1

公开(公告)日：2017-11-30

申请号：US15169262

申请日：2016-05-31

Applicant: Intel Corporation

Inventor： VIDHYA KRISHNAN ,  BALAJI VEMBU ,  SANDEEP S. SODHI ,  PRIYADARSINI DEVANAND

IPC: H04N7/167 ,  H04L9/06

CPC classification number: H04N7/1675 ,  H04L9/065 ,  H04L2209/125 ,  H04L2209/34 ,  H04L2209/60 ,  H04N21/2347

Abstract: Apparatuses, methods and storage medium associated with single pass parallel encryption are disclosed herein. In embodiments, an apparatus for computing may comprise an encryption engine to encrypt a video stream. The encryption engine may comprise a plurality of encryption pipelines to respectively encrypt a plurality of video sub-streams partitioned from the video stream in parallel in a single pass as the video sub-streams are being generated. The plurality of encryption pipelines may use a corresponding plurality of multi-part encryption counters to encrypt the corresponding video sub-streams as the video sub-streams are being generated. Each of the multi-part encryption counters used by one of the encryption pipelines may comprise a sub-portion that remains constant while encoding the corresponding video sub-stream, but the sub-key is unique for the one encryption pipeline, and differs from corresponding sub-portions of the multi-part encryption counters used by the other encryption pipelines. Other embodiments may be disclosed or claimed.