公开(公告)号：US20240183884A1

公开(公告)日：2024-06-06

申请号：US18076352

申请日：2022-12-06

Applicant: Intel Corporation

Inventor： Vikrant Thigle ,  Vijay Anand Mathiyalagan ,  Anand Haridass ,  Arun Chandrasekhar ,  Gerald Pasdast

IPC: G01R19/00 ,  G01R19/25 ,  G05F1/46

CPC classification number: G01R19/0038 ,  G01R19/25 ,  G05F1/46

Abstract: Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.

公开(公告)号：US20220415742A1

公开(公告)日：2022-12-29

申请号：US17356239

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bijoyraj Sahu ,  Tolga Acikalin ,  Anand Haridass ,  Vikrant Thigle

IPC: H01L23/34 ,  H01L23/36 ,  H01L23/48

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, and a die, electrically coupled to the package substrate, including a silicon substrate having a first surface and an opposing second surface; a device layer at the first surface of the silicon substrate; and a dielectric layer, having a heater trace, at the second surface of the silicon substrate.