公开(公告)号：US10854245B1

公开(公告)日：2020-12-01

申请号：US16514780

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Setul M. Shah ,  William Sheung ,  Dhruval J. Patel

IPC: G11C5/14 ,  G11C16/10 ,  H02M3/07 ,  G05F1/575 ,  G11C16/30

Abstract: Techniques to adapt the DC bias of voltage regulators for memory devices as a function of bandwidth demand are described. In one example, a non-volatile memory device includes a plurality of voltage regulator slices, wherein outputs of the plurality of voltage regulators slices are tied together to provide a voltage to perform operations on the array. The voltage regulator slices can be enabled or disabled based on a signal from a memory controller, such as an indication of an upcoming change in bandwidth demand for a rank including the memory device.

公开(公告)号：US20230051899A1

公开(公告)日：2023-02-16

申请号：US17399925

申请日：2021-08-11

Applicant: Intel Corporation

Inventor： Yuchen Hu ,  William Sheung

IPC: G11C13/00 ,  G06F3/06

Abstract: An apparatus comprising an input to couple to a negative voltage source; and circuitry to detect whether the input has crossed a negative voltage threshold, wherein the circuitry comprises a first capacitor that is selectively coupled to the first input and a second capacitor that is selectively coupled to a second input coupled to a positive voltage source.