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公开(公告)号：US20190278503A1
公开(公告)日：2019-09-12
申请号：US16425883
申请日：2019-05-29
Applicant: Intel Corporation
Inventor： Sowmiya JAYACHANDRAN , Andrew MORNING-SMITH , Brian R. MCFARLANE , William T. GLENNAN , Emily P. CHUNG
Abstract: A method is described. The method includes performing write operations on a plurality of NVRAM semiconductor chips of a memory module while tracking power budget headroom for performing the write operations and while monitoring current draw on a supply voltage rail that is coupled to the plurality of NVRAM semiconductor chips. The method further includes detecting the current draw has reached a threshold. The method further includes ceasing or diminishing the write operations in response to the detecting.
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公开(公告)号：US20170307694A1
公开(公告)日：2017-10-26
申请号：US15529332
申请日：2015-11-20
Applicant: Intel Corporation
Inventor： Naoki MATSUMURA , Allen HUANG , Gang JI , Brian C. FRITZ , William T. GLENNAN , Ramakrishna Ram PALLALA , Hung T. TRAN
CPC classification number: G01R31/392 , G01K1/00 , G01R31/3648 , G01R31/371 , G01R31/374 , G01R31/382 , G01S5/0027 , G01S19/42
Abstract: In embodiments, an apparatus may include a battery life monitor. The battery life monitor may, in some embodiments, receive a battery level indicator indicative of a current charge level of a battery that is coupled with the apparatus and a first temperature that may indicate a temperature of a current location of the apparatus. The battery life monitor may also receive one or more additional temperatures that indicate respective temperatures of one or more locations in which the apparatus is likely to be operated prior to discharge of the current charge level of the battery. Based at least in part on the current charge level, the first temperature indicator, and the one or more additional temperatures, the battery life monitor may calculate one or more battery life estimates that correspond with the one or more locations. Other embodiments may be described and/or claimed.
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