公开(公告)号：US20190278503A1

公开(公告)日：2019-09-12

申请号：US16425883

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Sowmiya JAYACHANDRAN ,  Andrew MORNING-SMITH ,  Brian R. MCFARLANE ,  William T. GLENNAN ,  Emily P. CHUNG

IPC: G06F3/06 ,  G06F1/30 ,  G06F11/30

Abstract: A method is described. The method includes performing write operations on a plurality of NVRAM semiconductor chips of a memory module while tracking power budget headroom for performing the write operations and while monitoring current draw on a supply voltage rail that is coupled to the plurality of NVRAM semiconductor chips. The method further includes detecting the current draw has reached a threshold. The method further includes ceasing or diminishing the write operations in response to the detecting.

公开(公告)号：US20200034061A1

公开(公告)日：2020-01-30

申请号：US16585801

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Sahar KHALILI ,  Zvika GREENFIELD ,  Sowmiya JAYACHANDRAN ,  Robert J. ROYER, JR. ,  Dimpesh PATEL

IPC: G06F3/06 ,  G06F12/0862

Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.

公开(公告)号：US20180068695A1

公开(公告)日：2018-03-08

申请号：US15703589

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant S. DAMLE ,  Frank T. HADY ,  Paul D. RUBY ,  Kiran PANGAL ,  Sowmiya JAYACHANDRAN

IPC: G11C7/10 ,  G11C11/406 ,  G11C16/34

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3431

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.