公开(公告)号：US20240195749A1

公开(公告)日：2024-06-13

申请号：US18424376

申请日：2024-01-26

Applicant: Intel Corporation

Inventor： Anurag AGRAWAL ,  John Andrew FINGERHUT ,  Xiaoyan DING ,  Song ZHANG

IPC: H04L47/628 ,  H04L45/24 ,  H04L49/00

CPC classification number: H04L47/628 ,  H04L45/24 ,  H04L49/3063

Abstract: Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.

公开(公告)号：US20240080276A1

公开(公告)日：2024-03-07

申请号：US18503851

申请日：2023-11-07

Applicant: Intel Corporation

Inventor： Anurag AGRAWAL ,  John Andrew FINGERHUT ,  Xiaoyan DING ,  Song ZHANG

IPC: H04L47/628 ,  H04L45/24 ,  H04L49/00

CPC classification number: H04L47/628 ,  H04L45/24 ,  H04L49/3063

Abstract: Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.

公开(公告)号：US20220109639A1

公开(公告)日：2022-04-07

申请号：US17550938

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Anurag AGRAWAL ,  John Andrew FINGERHUT ,  Xiaoyan DING ,  Song ZHANG

IPC: H04L47/628 ,  H04L45/24 ,  H04L49/00

Abstract: Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.