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公开(公告)号：US20190095229A1
公开(公告)日：2019-03-28
申请号：US15713301
申请日：2017-09-22
Applicant: Intel Corporation
Inventor： XIANGYANG GUO , SIMONJIT DUTTA , HAN LEE , YIPENG WANG
CPC classification number: G06F9/4552 , G06F8/41 , G06F8/44
Abstract: Methods, apparatus, systems, and articles of manufacture to facilitate field-programmable gate array support during runtime execution of computer readable instructions are disclosed herein. An example apparatus includes a compiler to, prior to runtime, compile a block of code written as high level source code into a first hardware bitstream kernel and a second hardware bitstream kernel; a kernel selector to select the first hardware bitstream kernel based on an attribute to be dispatched during runtime; a dispatcher to dispatch the first hardware bitstream kernel to a field programmable gate array (FPGA) during runtime; and the kernel selector to, when an FPGA attribute does not satisfy a threshold during runtime, adjust the selection of the first hardware bitstream kernel to the second hardware bitstream kernel to be dispatched during runtime.
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公开(公告)号：US20210406147A1
公开(公告)日：2021-12-30
申请号：US16914305
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： BIN LI , REN WANG , KSHITIJ ARUN DOSHI , FRANCESC GUIM BERNAT , YIPENG WANG , RAVISHANKAR IYER , ANDREW HERDRICH , TSUNG-YUAN TAI , ZHU ZHOU , RASIKA SUBRAMANIAN
Abstract: An apparatus and method for closed loop dynamic resource allocation. For example, one embodiment of a method comprises: collecting data related to usage of a plurality of resources by a plurality of workloads over one or more time periods, the workloads including priority workloads associated with one or more guaranteed performance levels and best effort workloads not associated with guaranteed performance levels; analyzing the data to identify resource reallocations from one or more of the priority workloads to one or more of the best effort workloads in one or more subsequent time periods while still maintaining the guaranteed performance levels; reallocating the resources from the priority workloads to the best effort workloads for the subsequent time periods; monitoring execution of the priority workloads with respect to the guaranteed performance level during the subsequent time periods; and preemptively reallocating resources from the best effort workloads to the priority workloads during the subsequent time periods to ensure compliance with the guaranteed performance level and responsive to detecting that the guaranteed performance level is in danger of being breached.
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3.发明申请公开(公告)号：US20200081835A1
公开(公告)日：2020-03-12
申请号：US16126907
申请日：2018-09-10
Applicant: Intel Corporation
Inventor： REN WANG , RAANAN SADE , YIPENG WANG , Tsung-Yuan TAI , SAMEH GOBRIEL
IPC: G06F12/0811 , G06F17/30 , G06F9/38
Abstract: An apparatus and method for prioritizing transactional memory regions. For example, one embodiment of a processor comprises: a plurality of cores to execute threads comprising sequences of instructions, at least some of the instructions specifying a transactional memory region; a cache of each core to store a plurality of cache lines; transactional memory circuitry of each core to manage execution of the transactional memory (TM) regions based on priorities associated with each of the TM regions; and wherein the transactional memory circuitry, upon detecting a conflict between a first TM region having a first priority value and a second TM region having a second priority value, is to determine which of the first TM region or the second TM region is permitted to continue executing and which is to be aborted based, at least in part, on the first and second priority values.
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