公开(公告)号：US20190116129A1

公开(公告)日：2019-04-18

申请号：US16218262

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： REN WANG ,  AHMAD A. SAMIH ,  CHRISTIAN MACIOCCO ,  ANDREW BROWN ,  TSUNG-YUAN C. TAI

IPC: H04L12/927 ,  H04L12/725 ,  H04L12/931 ,  H04L12/24 ,  H04L12/851 ,  H04L12/841 ,  H04L12/863

Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for routing data packets in a quality of service (QoS) enabled content-based network or interconnect fabric. Various embodiments describe how to manage data flow based on content-based attribute vectors (AVs) indicating QoS requirements with respect to the data packets in networking or platform interconnects. A dynamic scheduling based on AV information may improve trafficking efficiency and optimize system performance.

公开(公告)号：US20160182567A1

公开(公告)日：2016-06-23

申请号：US14582063

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： KAPIL SOOD ,  MANUEL NEDBAL ,  THOMAS M. SLAIGHT ,  BRIAN J. SKERRY ,  REN WANG

IPC: H04L29/06 ,  G06F17/30 ,  G06F21/55

CPC classification number: H04L63/20 ,  G06F21/554 ,  H04L63/0272 ,  H04L63/10 ,  H04L63/101 ,  H04L63/104 ,  H04L63/1441

Abstract: Examples may include techniques to securely provision, configure, and de-provision virtual network functions for a software defined network or a cloud infrastructure elements. A policy for a virtual network function may be received, at a secure execution partition of circuitry, and the virtual network function configured to implement the policy by the secure execution partition of the circuitry. The secure execution partition may connect to the virtual network function through a virtual switch and may cause the virtual network function to implement a network function based on the policy.

Abstract translation: 示例可以包括用于为软件定义的网络或云基础设施元件安全地提供，配置和去除虚拟网络功能的技术。 可以在电路的安全执行分区处接收用于虚拟网络功能的策略，并且被配置为通过电路的安全执行分区实现策略的虚拟网络功能。 安全执行分区可以通过虚拟交换机连接到虚拟网络功能，并且可以使虚拟网络功能基于策略实现网络功能。

公开(公告)号：US20210406147A1

公开(公告)日：2021-12-30

申请号：US16914305

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： BIN LI ,  REN WANG ,  KSHITIJ ARUN DOSHI ,  FRANCESC GUIM BERNAT ,  YIPENG WANG ,  RAVISHANKAR IYER ,  ANDREW HERDRICH ,  TSUNG-YUAN TAI ,  ZHU ZHOU ,  RASIKA SUBRAMANIAN

IPC: G06F11/34 ,  G06F9/50 ,  G06K9/62 ,  G06N20/00

Abstract: An apparatus and method for closed loop dynamic resource allocation. For example, one embodiment of a method comprises: collecting data related to usage of a plurality of resources by a plurality of workloads over one or more time periods, the workloads including priority workloads associated with one or more guaranteed performance levels and best effort workloads not associated with guaranteed performance levels; analyzing the data to identify resource reallocations from one or more of the priority workloads to one or more of the best effort workloads in one or more subsequent time periods while still maintaining the guaranteed performance levels; reallocating the resources from the priority workloads to the best effort workloads for the subsequent time periods; monitoring execution of the priority workloads with respect to the guaranteed performance level during the subsequent time periods; and preemptively reallocating resources from the best effort workloads to the priority workloads during the subsequent time periods to ensure compliance with the guaranteed performance level and responsive to detecting that the guaranteed performance level is in danger of being breached.

公开(公告)号：US20200081835A1

公开(公告)日：2020-03-12

申请号：US16126907

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： REN WANG ,  RAANAN SADE ,  YIPENG WANG ,  Tsung-Yuan TAI ,  SAMEH GOBRIEL

IPC: G06F12/0811 ,  G06F17/30 ,  G06F9/38

Abstract: An apparatus and method for prioritizing transactional memory regions. For example, one embodiment of a processor comprises: a plurality of cores to execute threads comprising sequences of instructions, at least some of the instructions specifying a transactional memory region; a cache of each core to store a plurality of cache lines; transactional memory circuitry of each core to manage execution of the transactional memory (TM) regions based on priorities associated with each of the TM regions; and wherein the transactional memory circuitry, upon detecting a conflict between a first TM region having a first priority value and a second TM region having a second priority value, is to determine which of the first TM region or the second TM region is permitted to continue executing and which is to be aborted based, at least in part, on the first and second priority values.

公开(公告)号：US20180270309A1

公开(公告)日：2018-09-20

申请号：US15722698

申请日：2017-10-02

Applicant: INTEL CORPORATION

Inventor： MESUT A. ERGIN ,  JR-SHIAN TSAI ,  JANET TSENG ,  REN WANG ,  JUN NAKAJIMA ,  TSUNG-YUAN TAI

IPC: H04L29/08 ,  H04L12/835 ,  H04L12/713 ,  H04L12/721 ,  H04L12/725 ,  H04L12/26

Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.

公开(公告)号：US20180109460A1

公开(公告)日：2018-04-19

申请号：US15473413

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： BYRON MAROHN ,  CHRISTIAN MACIOCCO ,  SAMEH GOBRIEL ,  REN WANG ,  TSUNG-YUAN C. TAI

IPC: H04L12/819 ,  H04L12/743

CPC classification number: H04L47/215 ,  H04L45/38 ,  H04L45/54 ,  H04L45/7453

Abstract: The present disclosure describes a process and apparatus for improving insertions of entries into a hash table. A large number of smaller virtual buckets may be combined together and associated with buckets used for hash table entry lookups and/or entry insertion. On insertion of an entry, hash table entries associated with a hashed-to virtual bucket may be moved between groups of buckets associated with the virtual bucket, to better distribute entries across the available buckets to reduce the number of entries in the largest buckets and the standard deviation of the bucket sizes across the entire hash table.

公开(公告)号：US20170054659A1

公开(公告)日：2017-02-23

申请号：US14830862

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： MESUT A. ERGIN ,  JR-SHIAN TSAI ,  JANET TSENG ,  REN WANG ,  JUN NAKAJIMA ,  TSUNG-YUAN TAI

IPC: H04L12/931 ,  H04L12/741 ,  H04L12/813 ,  H04L29/08 ,  H04L12/26

CPC classification number: H04L67/1097 ,  H04L43/103 ,  H04L45/306 ,  H04L45/38 ,  H04L45/586 ,  H04L47/30

Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.

Abstract translation: 各种实施例通常涉及用于提高在通信服务器内的VM对之间交换分组的效率的技术。 设备可以包括处理器组件; 用于将处理器组件耦合到网络的网络接口; 分析通过网络和通信服务器在端点设备之间交换的一组分组的至少一个分组的内容的虚拟交换机，并且基于多个虚拟服务器的一个或多个虚拟服务器来路由该组数据包 内容; 以及多个虚拟服务器的第一虚拟服务器的传送组件，以确定是否将该组数据包路由到虚拟交换机，或者以一种绕过该虚拟交换机的方式将该组数据包传送到多个虚拟服务器的第二虚拟服务器 基于路由规则的虚拟交换机。

公开(公告)号：US20160187958A1

公开(公告)日：2016-06-30

申请号：US14582993

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： REN WANG ,  CHRISTIAN MACIOCCO ,  PATRICK CONNOR ,  DINESH KUMAR ,  NRUPAL JANI ,  DANIEL DAHLE ,  SAMEH GOBRIEL

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/3287 ,  G06F1/3278 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to create an idle period for a processing unit and a switching circuit by buffering one or more packets in a buffer for one or more input/output (I/O) ports. Embodiments may include causing the processing unit and/or the switching circuit to operate in a lower power state during the idle period and causing the processing unit and/or the switching circuit to exit the lower power state by communicating one or more out-of-band messages to the processing unit and/or the switching circuit.

Abstract translation: 各种实施例通常涉及通过缓冲一个或多个输入/输出（I / O）端口的缓冲器中的一个或多个分组来为处理单元和切换电路创建空闲周期的装置，方法和其他技术。 实施例可以包括使得处理单元和/或开关电路在空闲周期期间以较低功率状态工作，并且使处理单元和/或开关电路通过传送一个或多个外部电源而退出低功率状态， 频带消息到处理单元和/或开关电路。

公开(公告)号：US20230126783A1

公开(公告)日：2023-04-27

申请号：US18089171

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： JIAYU HU ,  REN WANG ,  XUAN DING ,  CHENG JIANG ,  CUNMING LIANG ,  NARAYAN RANGANATHAN ,  RAJESH SANKARAN ,  XIAO WANG

IPC: G06F12/1018 ,  G06F16/22

Abstract: A processor may determine, based on a length of an input key, whether to compute a hash value based on the input key or cause an accelerator device coupled to the processor to compute the hash value based on the input key. The processor may cause a hash table lookup operation to be performed based on the hash value.

公开(公告)号：US20170054658A1

公开(公告)日：2017-02-23

申请号：US14830856

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： ALEXANDER W. MIN ,  TSUNG-YUAN TAI ,  REN WANG ,  MESUT A. ERGIN ,  JR-SHIAN TSAI

IPC: H04L12/931 ,  H04L12/26 ,  H04L12/741 ,  H04L29/08

CPC classification number: H04L49/70 ,  G06F9/46 ,  H04L43/0852 ,  H04L43/103 ,  H04L43/16 ,  H04L45/38 ,  H04L45/586 ,  H04L45/74 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/80 ,  H04L49/25

Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets among multiple VMs within a communications server, and between the communications server and other devices in a communications system. An apparatus may include a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through a network, and to correlate the contents to a pathway to extend through one or more of the VMs that are each configured as virtual servers of multiple virtual servers; and an interface control component to select at least one virtual network interface of each of the one or more virtual servers along the pathway to operate in a polling mode, and to select a virtual network interface of at least one virtual server of the multiple virtual servers not along the pathway to operate in a non-polling mode.

Abstract translation: 各种实施例通常涉及用于提高在通信服务器内的多个VM之间以及通信服务器和通信系统中的其他设备之间交换分组的效率的技术。 一种装置可以包括虚拟交换机，用于分析要通过网络在端点设备之间交换的一组分组的至少一个分组的内容，并且将该内容与通过一个或多个虚拟机的路径相关联， 配置为多个虚拟服务器的虚拟服务器; 以及接口控制组件，用于选择所述一个或多个虚拟服务器中的每一个的至少一个虚拟网络接口沿着所述路径以轮询模式操作，并且选择所述多个虚拟服务器中的至少一个虚拟服务器的虚拟网络接口 不是在非轮询模式下运行的途径。