公开(公告)号：US20200081835A1

公开(公告)日：2020-03-12

申请号：US16126907

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： REN WANG ,  RAANAN SADE ,  YIPENG WANG ,  Tsung-Yuan TAI ,  SAMEH GOBRIEL

IPC: G06F12/0811 ,  G06F17/30 ,  G06F9/38

Abstract: An apparatus and method for prioritizing transactional memory regions. For example, one embodiment of a processor comprises: a plurality of cores to execute threads comprising sequences of instructions, at least some of the instructions specifying a transactional memory region; a cache of each core to store a plurality of cache lines; transactional memory circuitry of each core to manage execution of the transactional memory (TM) regions based on priorities associated with each of the TM regions; and wherein the transactional memory circuitry, upon detecting a conflict between a first TM region having a first priority value and a second TM region having a second priority value, is to determine which of the first TM region or the second TM region is permitted to continue executing and which is to be aborted based, at least in part, on the first and second priority values.

公开(公告)号：US20180109460A1

公开(公告)日：2018-04-19

申请号：US15473413

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： BYRON MAROHN ,  CHRISTIAN MACIOCCO ,  SAMEH GOBRIEL ,  REN WANG ,  TSUNG-YUAN C. TAI

IPC: H04L12/819 ,  H04L12/743

CPC classification number: H04L47/215 ,  H04L45/38 ,  H04L45/54 ,  H04L45/7453

Abstract: The present disclosure describes a process and apparatus for improving insertions of entries into a hash table. A large number of smaller virtual buckets may be combined together and associated with buckets used for hash table entry lookups and/or entry insertion. On insertion of an entry, hash table entries associated with a hashed-to virtual bucket may be moved between groups of buckets associated with the virtual bucket, to better distribute entries across the available buckets to reduce the number of entries in the largest buckets and the standard deviation of the bucket sizes across the entire hash table.

公开(公告)号：US20160187958A1

公开(公告)日：2016-06-30

申请号：US14582993

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： REN WANG ,  CHRISTIAN MACIOCCO ,  PATRICK CONNOR ,  DINESH KUMAR ,  NRUPAL JANI ,  DANIEL DAHLE ,  SAMEH GOBRIEL

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/3287 ,  G06F1/3278 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to create an idle period for a processing unit and a switching circuit by buffering one or more packets in a buffer for one or more input/output (I/O) ports. Embodiments may include causing the processing unit and/or the switching circuit to operate in a lower power state during the idle period and causing the processing unit and/or the switching circuit to exit the lower power state by communicating one or more out-of-band messages to the processing unit and/or the switching circuit.

Abstract translation: 各种实施例通常涉及通过缓冲一个或多个输入/输出（I / O）端口的缓冲器中的一个或多个分组来为处理单元和切换电路创建空闲周期的装置，方法和其他技术。 实施例可以包括使得处理单元和/或开关电路在空闲周期期间以较低功率状态工作，并且使处理单元和/或开关电路通过传送一个或多个外部电源而退出低功率状态， 频带消息到处理单元和/或开关电路。