公开(公告)号：US20180285305A1

公开(公告)日：2018-10-04

申请号：US15476513

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Yonah LASKER

IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

CPC classification number: G06F13/42 ,  G06F13/36 ,  G06F13/4022

Abstract: Techniques and mechanisms for providing test functionality at an integrated circuit (IC) chip. In an embodiment, the IC chip includes protocol stacks variously coupled each between a switch fabric and other switch circuitry which is configurable to selectively implement, at least in part, either of an operational mode and a test mode. The operational mode facilitates communication, via the switch circuitry, between a first protocol stack and physical layer circuitry. The test mode instead enables communication, between the first protocol stack and a second protocol stack, of test packet information which is based on a test packet received from the switch fabric. In another embodiment, the protocol stacks support communication according to a Thunderbolt™ protocol.