公开(公告)号：US20230028666A1

公开(公告)日：2023-01-26

申请号：US17379121

申请日：2021-07-19

申请人： Intel Corporation

发明人： Joydeep Ray ,  Prathamesh Raghunath Shinde ,  Yue Qi ,  Abhishek R. Appu ,  Xinmin Tian ,  Vasanth Ranganathan ,  Ben J. Ashbaugh

IPC分类号： G06F9/30

摘要： Embodiments are directed to systems and methods for performing global memory atomics in a private cache of a sub-core of a GPU. An embodiment of a GPU includes multiple sub-cores each including a load/store pipeline. The load/store pipeline is operable to receive information specifying an atomic operation to be performed within a primary data cache of the load/store pipeline. The load/store pipeline is also operable to read data to be modified by the atomic operation into the primary data cache from a memory hierarchy shared by the multiple sub-cores. The load/store pipeline is further operable to produce an atomic result of the atomic operation by modifying the data within the primary data cache based on the atomic operation.

公开(公告)号：US20220414054A1

公开(公告)日：2022-12-29

申请号：US17304797

申请日：2021-06-25

申请人： Intel Corporation

发明人： Jorge Parra ,  Jiasheng Chen ,  Supratim Pal ,  Fangwen Fu ,  Sabareesh Ganapathy ,  Chandra Gurram ,  Chunhui Mei ,  Yue Qi

IPC分类号： G06F15/80 ,  G06F9/38

摘要： A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.