公开(公告)号：US20240304473A1

公开(公告)日：2024-09-12

申请号：US18179092

申请日：2023-03-06

Applicant: Intel Corporation

Inventor： Zewei Wang ,  George Frank Robinson, JR. ,  Tingting Gao ,  Viet Chau

IPC: H01L21/67 ,  H01L21/48

CPC classification number: H01L21/67121 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838

Abstract: Methods, apparatus, systems, and articles of manufacture to place balls for second level interconnects of integrated circuit packages are disclosed. An example apparatus includes a ball head including a first surface having an array of holes. The array of holes hold a corresponding array of solder balls to be placed on a package substrate of an integrated circuit package. The apparatus also includes a protrusion extending away from the surface of the ball head. The protrusion is positioned relative to the holes to contact a second surface of the package substrate when the solder balls are to be placed on the package substrate.

公开(公告)号：US20250006691A1

公开(公告)日：2025-01-02

申请号：US18345695

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： George Robinson ,  Mohamed Elhebeary ,  Divya Jain ,  Viet Chau ,  Zewei Wang ,  Mukund Ayalasomayajula ,  Suraj Maganty ,  Tingting Gao ,  Andrew Wayne Carlson ,  Khalid Mohammad Abdelaziz ,  Craig Jerome Madison ,  Edvin Cetegen ,  Joseph Petrini

IPC: H01L23/00

Abstract: Compliant inserts for pin dipping processes are disclosed herein. An example apparatus disclosed herein includes a pin array to transfer material to a package substrate of an integrated circuit package, a cover plate, an elastic insert to be disposed between the cover plate and the pin array.