公开(公告)号：US11526279B2

公开(公告)日：2022-12-13

申请号：US15930035

申请日：2020-05-12

Applicant: Intel Corporation

Inventor： Zion Kwok ,  Jawad Khan ,  Richard Coulson

IPC: G06F3/06 ,  G06F7/72

Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

公开(公告)号：US20220179582A1

公开(公告)日：2022-06-09

申请号：US17678865

申请日：2022-02-23

Applicant: Intel Corporation

Inventor： Zion Kwok ,  Santhosh Vanaparthy ,  Ravi Motwani ,  Poovaiah Manavattira Palangappa

IPC: G06F3/06

Abstract: An embodiment of an apparatus may comprise a controller coupled to one or more substrates and including circuitry to control access to NVM with a destructive read characteristic, perform a first read of a codeword from the NVM at a first reference voltage of a low confidence zone, perform a second read of the codeword from the NVM at a second reference voltage of the low confidence zone, and assign a lower confidence value to bits of the codeword that have a different value for the first read of the codeword and the second read of the codeword as compared to a confidence value assigned to bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword. Other embodiments are disclosed and claimed.

公开(公告)号：US20210399744A1

公开(公告)日：2021-12-23

申请号：US16904656

申请日：2020-06-18

Applicant: Intel Corporation

Inventor： Zion Kwok

IPC: H03M13/25 ,  G06F3/06 ,  G06F11/10

Abstract: Examples relate to a Low-Density Parity-Check Code (LDPC) decoder apparatus or device, to an LDPC decoder system and to corresponding methods and computer programs. The LDPC decoder apparatus comprises input circuitry and processing circuitry. The processing circuitry is configured to obtain a syndrome of a codeword via the input circuitry. The processing circuitry is configured to perform LDPC iterative decoding using the obtained syndrome, wherein the changes to be applied to the codeword due to the LDPC iterative decoding are recorded by applying the changes to a surrogate codeword. The processing circuitry is configured to record changes to be applied to the codeword due to the LDPC iterative decoding by storing the surrogate codeword in a memory structure.

公开(公告)号：US20200272340A1

公开(公告)日：2020-08-27

申请号：US15930035

申请日：2020-05-12

Applicant: Intel Corporation

Inventor： Zion Kwok ,  Jawad Khan ,  Richard Coulson

IPC: G06F3/06 ,  G06F7/72

Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.