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公开(公告)号：US10944428B2
公开(公告)日：2021-03-09
申请号：US16398003
申请日：2019-04-29
Applicant: Intel Corporation
Inventor： Ravi Motwani , Poovaiah Palangappa , Santhosh Vanaparthy
Abstract: Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.
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公开(公告)号：US20220179582A1
公开(公告)日：2022-06-09
申请号：US17678865
申请日：2022-02-23
Applicant: Intel Corporation
Inventor： Zion Kwok , Santhosh Vanaparthy , Ravi Motwani , Poovaiah Manavattira Palangappa
IPC: G06F3/06
Abstract: An embodiment of an apparatus may comprise a controller coupled to one or more substrates and including circuitry to control access to NVM with a destructive read characteristic, perform a first read of a codeword from the NVM at a first reference voltage of a low confidence zone, perform a second read of the codeword from the NVM at a second reference voltage of the low confidence zone, and assign a lower confidence value to bits of the codeword that have a different value for the first read of the codeword and the second read of the codeword as compared to a confidence value assigned to bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword. Other embodiments are disclosed and claimed.
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公开(公告)号：US20190260394A1
公开(公告)日：2019-08-22
申请号：US16398003
申请日：2019-04-29
Applicant: Intel Corporation
Inventor： Ravi Motwani , Poovaiah Palangappa , Santhosh Vanaparthy
Abstract: Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.
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