公开(公告)号：US20210067163A1

公开(公告)日：2021-03-04

申请号：US16958034

申请日：2018-03-30

Applicant: Intel IP Corporation

Inventor： Niranjan Karandikar ,  Mohammed Alam ,  Gregory Chance ,  Armando Cova ,  Michael Milyard ,  John J. Parkes, JR. ,  Ashoke Ravi ,  Daniel Schwartz ,  Dong-Jun Yang

IPC: H03L7/085 ,  H04B1/12 ,  H04L25/03 ,  H04B1/18 ,  H04L25/08

Abstract: A wireless communication device can include an antenna configured to sense a radio frequency (RF) signal. The wireless communication device can include signal estimation circuitry configured to generate estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include adder circuitry configured to subtract the spur cancellation signal from the RF signal to generate a spur cancelled signal.

公开(公告)号：US20210021272A1

公开(公告)日：2021-01-21

申请号：US16766921

申请日：2018-03-30

Applicant: Intel IP Corporation

Inventor： Niranjan Karandikar ,  Wayne Ballantyne ,  Gregory Chance ,  Simon Hughes ,  Daniel Schwartz ,  Nebil Tanzi

IPC: H03L7/099 ,  H03L7/093 ,  H03L7/091 ,  H03L7/185

Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

公开(公告)号：US20200321994A1

公开(公告)日：2020-10-08

申请号：US16956738

申请日：2018-03-28

Applicant: Intel IP Corporation

Inventor： Mohammed Alam ,  Yiwen Chen ,  Ricardo Fernandez ,  John J. Parkes, JR. ,  James Riches ,  Werner Schelmbauer ,  Daniel Schwartz ,  Michael David Vicker ,  Dong-Jun Yang

IPC: H04B1/26 ,  H04B1/18 ,  H04B7/0413 ,  H04B7/08 ,  H04L25/02

Abstract: A wireless communication device can include an antenna array configured to receive a plurality of radio frequency (RF) signals, RF circuitry, and digital baseband receive circuitry. The RF circuitry is configured to process the plurality of RF signals received via the antenna array to generate a single RF signal. The digital baseband receive circuitry is coupled to the RF circuitry and is configured to generate a downconverted signal based on the single RF signal, amplify the downconverted signal to generate an amplified downconverted signal, and convert the amplified downconverted signal to generate a digital output signal for processing by a wireless modem. The digital baseband receive circuitry further includes at least a first filtering system configured to filter the downconverted signal prior to amplification.