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1.发明申请公开(公告)号：US20190253058A1
公开(公告)日：2019-08-15
申请号：US16329312
申请日：2016-09-29
Applicant: INTEL IP CORPORATION
Inventor： Ashoke Ravi , Rotem Banin , Ofir Degani , David Ben-Haim , Yigal Kalmanovich
CPC classification number: H03L7/0995 , H03L7/093 , H03L2207/50 , H04L7/0331 , H04L7/08
Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
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公开(公告)号：US10230520B2
公开(公告)日：2019-03-12
申请号：US15586619
申请日：2017-05-04
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC: H04L27/152 , H04L7/033 , H04B7/06 , H04L27/20 , H04W88/06 , H03L7/16 , H04B7/0413 , H03K5/00
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US20170085365A1
公开(公告)日：2017-03-23
申请号：US14861132
申请日：2015-09-22
Applicant: Intel IP Corporation
Inventor： Ashoke Ravi , Ofir Degani , Rotem Banin , Assaf Ben-Bassat
CPC classification number: H04L7/042 , G04F10/005 , H03K5/135 , H03M1/1061 , H03M1/82 , H04B1/0475 , H04L7/0054
Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.
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公开(公告)号：US09331722B2
公开(公告)日：2016-05-03
申请号：US14140801
申请日：2013-12-26
Applicant: Intel IP Corporation
Inventor： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
CPC classification number: H04B17/21 , H03F1/3241 , H03M1/1009 , H03M1/82 , H03M1/84 , H04B1/0475 , H04B2001/0425
Abstract: This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.
Abstract translation: 本文讨论了用于补偿数字到时间转换器（DTC）的非线性的装置和方法。 在一个示例中，无线设备可以包括被配置为从基带处理器接收相位数据信息并提供用于生成无线信号的第一调制信号的数字 - 时间转换器（DTC），检测器配置为接收第一 调制信号并提供DTC的非线性指示，以及被配置为使用非线性指示向DTC提供预失真信息的预失真模块。
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公开(公告)号：US11290065B2
公开(公告)日：2022-03-29
申请号：US16650882
申请日：2017-12-29
Applicant: Intel IP Corporation
Inventor： Ali Azam , Ashoke Ravi , Bassam Khamaisi , Ofir Degani
Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.
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Patent Agency Ranking
公开(公告)号：US11245403B2
公开(公告)日：2022-02-08
申请号：US16618427
申请日：2017-07-17
Applicant: INTEL IP CORPORATION
Inventor： Sebastian Sievert , Ofir Degani , Ashoke Ravi
Abstract: A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.
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公开(公告)号：US20210067163A1
公开(公告)日：2021-03-04
申请号：US16958034
申请日：2018-03-30
Applicant: Intel IP Corporation
Inventor： Niranjan Karandikar , Mohammed Alam , Gregory Chance , Armando Cova , Michael Milyard , John J. Parkes, JR. , Ashoke Ravi , Daniel Schwartz , Dong-Jun Yang
Abstract: A wireless communication device can include an antenna configured to sense a radio frequency (RF) signal. The wireless communication device can include signal estimation circuitry configured to generate estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include adder circuitry configured to subtract the spur cancellation signal from the RF signal to generate a spur cancelled signal.
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公开(公告)号：US10516563B2
公开(公告)日：2019-12-24
申请号：US15753551
申请日：2015-09-25
Applicant: Intel IP Corporation
Inventor： Sebastian Sievert , Ofir Degani , Ashoke Ravi , Rotem Banin
Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
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公开(公告)号：US09660798B2
公开(公告)日：2017-05-23
申请号：US14997056
申请日：2016-01-15
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC: H04L27/36 , H04L27/12 , H04L7/033 , H04B7/06 , H04L27/20 , H04W88/06 , H03L7/16 , H04B7/0413 , H04L27/152 , H03K5/00
CPC classification number: H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US10181856B2
公开(公告)日：2019-01-15
申请号：US15395504
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
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