公开(公告)号：US20200043874A1

公开(公告)日：2020-02-06

申请号：US16051376

申请日：2018-07-31

Applicant: INTEL IP CORPORATION

Inventor： Daniel Sira ,  Domagoj Siprak ,  Jonas Fritzin

IPC: H01L23/66 ,  G06F17/50 ,  H01L49/02 ,  H01L23/522 ,  H01L23/482 ,  H01L27/06

Abstract: An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.

公开(公告)号：US09490834B2

公开(公告)日：2016-11-08

申请号：US15048143

申请日：2016-02-19

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Michael Fulde ,  Daniel Sira ,  Gerhard Knoblinger

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/662

Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval. The first voltage is higher than an upper threshold voltage corresponding to a first digital threshold level of the digital input signal and the second voltage is lower than a lower threshold voltage corresponding to a second digital threshold level of the digital input signal. The third voltage is constantly between the upper threshold voltage and the lower threshold voltage.

Abstract translation: 提供了包括多个数模转换器单元的数模转换器电路。 多个数模转换器单元中的第一数模转换器单元包括单元控制模块，其被配置为交替地向第一数字到第一数模转换单元的电容元件的第一电极提供第一电压和第二电压， 基于数字输入信号在预定义的时间间隔内。 多个数模转换器单元的第二数模转换器单元包括单元控制模块，其被配置为在第二数模转换器单元的电容元件的第一电极处提供第三电压 预定义的时间间隔。 第一电压高于对应于数字输入信号的第一数字阈值电平的上阈值电压，而第二电压低于对应于数字输入信号的第二数字阈值电平的下阈值电压。 第三电压恒定在上阈值电压和较低阈值电压之间。

公开(公告)号：US20160285470A1

公开(公告)日：2016-09-29

申请号：US15048143

申请日：2016-02-19

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Michael Fulde ,  Daniel Sira ,  Gerhard Knoblinger

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/662

Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval. The first voltage is higher than an upper threshold voltage corresponding to a first digital threshold level of the digital input signal and the second voltage is lower than a lower threshold voltage corresponding to a second digital threshold level of the digital input signal. The third voltage is constantly between the upper threshold voltage and the lower threshold voltage.

Abstract translation: 提供了包括多个数模转换器单元的数模转换器电路。 多个数模转换器单元中的第一数模转换器单元包括单元控制模块，其被配置为交替地向第一数字到第一数模转换单元的电容元件的第一电极提供第一电压和第二电压， 基于数字输入信号在预定义的时间间隔内。 多个数模转换器单元的第二数模转换器单元包括单元控制模块，其被配置为在第二数模转换器单元的电容元件的第一电极处提供第三电压 预定义的时间间隔。 第一电压高于对应于数字输入信号的第一数字阈值电平的上阈值电压，而第二电压低于对应于数字输入信号的第二数字阈值电平的下阈值电压。 第三电压恒定在上阈值电压和较低阈值电压之间。