公开(公告)号：US20190214944A1

公开(公告)日：2019-07-11

申请号：US16321308

申请日：2016-09-26

Applicant: Intel IP Corporation

Inventor： Georgios Yorgos Palaskas ,  Paolo Madoglio ,  Dirk Friedrich

IPC: H03B19/12 ,  H03C3/09 ,  H03C5/00 ,  H03M1/86 ,  H04B1/04

Abstract: Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

公开(公告)号：US09641185B1

公开(公告)日：2017-05-02

申请号：US15199217

申请日：2016-06-30

Applicant: INTEL IP CORPORATION

Inventor： Georgios Yorgos Palaskas ,  Paolo Madoglio ,  Peter Preyler ,  Rotem Banin

IPC: H03M1/66 ,  H03M1/06 ,  H03M7/42 ,  H03M1/46

CPC classification number: H03M1/06 ,  H03F3/195 ,  H03F3/24 ,  H03M1/466 ,  H03M1/68 ,  H03M1/82 ,  H03M5/02 ,  H03M7/42

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

公开(公告)号：US10886878B2

公开(公告)日：2021-01-05

申请号：US16321308

申请日：2016-09-26

Applicant: Intel IP Corporation

Inventor： Georgios Yorgos Palaskas ,  Paolo Madoglio ,  Dirk Friedrich

IPC: H03B19/12 ,  H03C5/00 ,  H03M1/86 ,  H04B1/04 ,  H03C3/09

Abstract: Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

公开(公告)号：US10177774B2

公开(公告)日：2019-01-08

申请号：US15583063

申请日：2017-05-01

Applicant: INTEL IP CORPORATION

Inventor： Georgios Yorgos Palaskas ,  Paolo Madoglio ,  Peter Preyler ,  Rotem Banin

IPC: H03M1/66 ,  H03M1/06 ,  H03M1/46 ,  H03M7/42 ,  H03F3/195 ,  H03F3/24 ,  H03M1/68 ,  H03M1/82 ,  H03M5/02

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

公开(公告)号：US20180006658A1

公开(公告)日：2018-01-04

申请号：US15583063

申请日：2017-05-01

Applicant: INTEL IP CORPORATION

Inventor： Georgios Yorgos Palaskas ,  Paolo Madoglio ,  Peter Preyler ,  Rotem Banin

IPC: H03M1/06 ,  H03M7/42 ,  H03M1/46

CPC classification number: H03M1/06 ,  H03F3/195 ,  H03F3/24 ,  H03M1/466 ,  H03M1/68 ,  H03M1/82 ,  H03M5/02 ,  H03M7/42

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.