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公开(公告)号：US09768809B2
公开(公告)日：2017-09-19
申请号：US14318829
申请日：2014-06-30
Applicant: Intel IP Corporation
Inventor： Stefan Tertinek , Peter Preyler , Thomas Mayer
CPC classification number: H04B1/0082 , G04F10/005
Abstract: This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.
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公开(公告)号：US20200280318A1
公开(公告)日：2020-09-03
申请号：US16646746
申请日：2017-09-12
Applicant: INTEL IP CORPORATION
Inventor： Christoph S. Preissi , Peter Preyler , Thomas Mayer
Abstract: Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.
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公开(公告)号：US09641185B1
公开(公告)日：2017-05-02
申请号：US15199217
申请日：2016-06-30
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
CPC classification number: H03M1/06 , H03F3/195 , H03F3/24 , H03M1/466 , H03M1/68 , H03M1/82 , H03M5/02 , H03M7/42
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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4.发明授权Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for generating a processed oscillator signal, an apparatus for generating a processed oscillator signal, and software-related implementations 有权电路，集成电路，发射器，接收器，收发器，用于产生经处理的振荡器信号的方法，用于产生经处理的振荡器信号的装置以及软件相关实现公开(公告)号：US09438259B2
公开(公告)日：2016-09-06
申请号：US14832342
申请日：2015-08-21
Applicant: Intel IP Corporation
Inventor： Stefan Tertinek , Peter Preyler , Thomas Mayer
CPC classification number: H03M1/10 , G06F1/0321 , H03L7/00 , H03L2207/50 , H03M1/82
Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.
Abstract translation: 根据示例的电路包括数字 - 时间转换器，其被配置为响应于控制信号接收振荡器信号并且基于接收的振荡器信号产生经处理的振荡器信号，以及时间交织控制电路，被配置为产生 基于时间交织技术的控制信号。
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公开(公告)号：US10979056B2
公开(公告)日：2021-04-13
申请号：US16646746
申请日：2017-09-12
Applicant: INTEL IP CORPORATION
Inventor： Christoph S. Preissel , Peter Preyler , Thomas Mayer
Abstract: Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.
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Patent Agency Ranking
6.发明授权Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for obtaining calibration data and a method for generating a local oscillator signal 有权电路，集成电路，发送器，接收器，收发器，用于获得校准数据的方法以及用于产生本地振荡器信号的方法公开(公告)号：US09537585B2
公开(公告)日：2017-01-03
申请号：US14620488
申请日：2015-02-12
Applicant: Intel IP Corporation
Inventor： Thomas Mayer , Stefan Tertinek , Peter Preyler
CPC classification number: H04B17/21 , H03L7/1976 , H04B1/62
Abstract: A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.
Abstract translation: 根据示例的电路包括数字 - 时间转换器和耦合到数字 - 时间转换器并被配置为产生从提供给信号处理电路的信号导出的处理信号的信号处理电路，处理信号包括 相对于提供给信号处理电路的信号的预定相位关系，其中电路被配置为接收参考信号并且基于接收到的参考信号产生输出信号。 测量电路被配置为测量输出信号和参考信号之间的延迟，其中数字 - 时间转换器的输出耦合到存储器，该存储器被配置为存储数字 - 时间转换器的校准数据，基于 测量延迟。
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7.发明申请NOISE-SHAPING CIRCUIT, DIGITAL-TO-TIME CONVERTER, ANALOG-TO-DIGITAL CONVERTER, DIGITAL-TO-ANALOG CONVERTER FREQUENCY SYNTHESIZER, TRANSMITTER, RECEIVER, TRANSCEIVER, METHOD FOR SHAPING NOISE IN AN INPUT SIGNAL 有权噪声形成电路，数字到时间转换器，模拟数字转换器，数字到模拟转换器频率合成器，发送器，接收器，收发器，在输入信号中形成噪声的方法公开(公告)号：US20160182072A1
公开(公告)日：2016-06-23
申请号：US14856854
申请日：2015-09-17
Applicant: Intel IP Corporation
Inventor： Peter Preyler , Thomas Mayer , Stefan Tertinek
CPC classification number: H03L7/20 , H03L7/16 , H03L2207/50 , H03M3/33 , H03M3/436
Abstract: A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.
Abstract translation: 根据示例的噪声整形电路包括被配置为基于输入信号生成输出信号的正向信号路径，被配置为基于输出信号将反馈信号反馈到前向信号路径的反馈信号路径，以及抖动 发生器被配置为产生抖动信号并将抖动信号耦合到正向信号路径中以修改输入信号并进入反馈信号路径。 使用根据示例的噪声整形电路可以提高整体噪声性能。
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8.发明申请CIRCUIT, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER, A TRANSCEIVER, A METHOD FOR GENERATING A PROCESSED OSCILLATOR SIGNAL, AN APPARATUS FOR GENERATING A PROCESSED OSCILLATOR SIGNAL, AND SOFTWARE-RELATED IMPLEMENTATIONS 有权电路，集成电路，发送器，接收器，收发器，产生处理的振荡器信号的方法，用于生成加工的振荡器信号的装置和与软件相关的实现公开(公告)号：US20160094237A1
公开(公告)日：2016-03-31
申请号：US14832342
申请日：2015-08-21
Applicant: Intel IP Corporation
Inventor： Stefan Tertinek , Peter Preyler , Thomas Mayer
CPC classification number: H03M1/10 , G06F1/0321 , H03L7/00 , H03L2207/50 , H03M1/82
Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.
Abstract translation: 根据示例的电路包括数字 - 时间转换器，其被配置为响应于控制信号接收振荡器信号并且基于接收的振荡器信号产生经处理的振荡器信号，以及时间交织控制电路，被配置为产生 基于时间交织技术的控制信号。
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公开(公告)号：US10177774B2
公开(公告)日：2019-01-08
申请号：US15583063
申请日：2017-05-01
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
IPC: H03M1/66 , H03M1/06 , H03M1/46 , H03M7/42 , H03F3/195 , H03F3/24 , H03M1/68 , H03M1/82 , H03M5/02
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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公开(公告)号：US20180006658A1
公开(公告)日：2018-01-04
申请号：US15583063
申请日：2017-05-01
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
CPC classification number: H03M1/06 , H03F3/195 , H03F3/24 , H03M1/466 , H03M1/68 , H03M1/82 , H03M5/02 , H03M7/42
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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