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公开(公告)号：US20170237549A1
公开(公告)日：2017-08-17
申请号：US15586619
申请日：2017-05-04
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
CPC classification number: H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US09641185B1
公开(公告)日：2017-05-02
申请号：US15199217
申请日：2016-06-30
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
CPC classification number: H03M1/06 , H03F3/195 , H03F3/24 , H03M1/466 , H03M1/68 , H03M1/82 , H03M5/02 , H03M7/42
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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公开(公告)号：US20160261401A1
公开(公告)日：2016-09-08
申请号：US14997056
申请日：2016-01-15
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC: H04L7/033 , H03L7/16 , H04L27/20 , H04B7/04 , H04L27/152
CPC classification number: H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US09288841B2
公开(公告)日：2016-03-15
申请号：US14138508
申请日：2013-12-23
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
CPC classification number: H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
Abstract translation: 本应用程序还讨论了用于在多个无线设备之间共享本地振荡器的装置和方法。 在某些示例中，装置可以包括配置成提供具有第一频率的中心振荡器信号的中央频率合成器，第一发射机，第一发射机包括被配置为接收中心振荡器的第一发射数字 - 时间转换器（DTC） 并且提供具有第二频率的第一发射机信号和第一接收机，所述第一接收机包括被配置为接收中心振荡器信号并提供具有第一接收频率的第一接收机信号的第一接收DTC。
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公开(公告)号：US10177774B2
公开(公告)日：2019-01-08
申请号：US15583063
申请日：2017-05-01
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
IPC: H03M1/66 , H03M1/06 , H03M1/46 , H03M7/42 , H03F3/195 , H03F3/24 , H03M1/68 , H03M1/82 , H03M5/02
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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Patent Agency Ranking
公开(公告)号：US20180006658A1
公开(公告)日：2018-01-04
申请号：US15583063
申请日：2017-05-01
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
CPC classification number: H03M1/06 , H03F3/195 , H03F3/24 , H03M1/466 , H03M1/68 , H03M1/82 , H03M5/02 , H03M7/42
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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公开(公告)号：US20190214944A1
公开(公告)日：2019-07-11
申请号：US16321308
申请日：2016-09-26
Applicant: Intel IP Corporation
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Dirk Friedrich
Abstract: Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.
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公开(公告)号：US09847676B2
公开(公告)日：2017-12-19
申请号：US14039996
申请日：2013-09-27
Applicant: Intel IP Corporation
Inventor： Paolo Madoglio , Georgios Palaskas , Bernd-Ulrich Klepser , Andreas Menkhoff , Zdravko Boos , Andreas Boehme , Michael Bruennert
CPC classification number: H02J50/20 , H02J7/025 , H02J17/00 , H02J50/90 , H04B1/0475 , H04L27/361 , H04W52/0251 , H04W52/028 , H04W52/52 , Y02D70/00 , Y02D70/40
Abstract: This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.
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公开(公告)号：US09660798B2
公开(公告)日：2017-05-23
申请号：US14997056
申请日：2016-01-15
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC: H04L27/36 , H04L27/12 , H04L7/033 , H04B7/06 , H04L27/20 , H04W88/06 , H03L7/16 , H04B7/0413 , H04L27/152 , H03K5/00
CPC classification number: H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US10886878B2
公开(公告)日：2021-01-05
申请号：US16321308
申请日：2016-09-26
Applicant: Intel IP Corporation
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Dirk Friedrich
Abstract: Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.
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