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1.
公开(公告)号:US11018114B2
公开(公告)日:2021-05-25
申请号:US16515979
申请日:2019-07-18
申请人: Intel IP Corporation
发明人: Bernd Waidhas , Georg Seidemann , Andreas Augustin , Laurent Millou , Andreas Wolter , Reinhard Mahnkopf , Stephan Stoeckl , Thomas Wagner
IPC分类号: H01L25/10 , H01L25/065 , H01L21/48 , H01L23/48 , H01L25/00 , H01L23/427 , G06F15/76
摘要: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
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公开(公告)号:US10727197B2
公开(公告)日:2020-07-28
申请号:US15464920
申请日:2017-03-21
申请人: Intel IP Corporation
发明人: Bernd Waidhas , Georg Seidemann , Andreas Wolter , Thomas Wagner , Stephan Stoeckl , Laurent Millou
IPC分类号: H01L25/065 , H01L23/538 , H01L23/498 , H01L23/00 , H01L21/56 , H01L25/00 , H01L21/683
摘要: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
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公开(公告)号:US10141265B2
公开(公告)日:2018-11-27
申请号:US15394388
申请日:2016-12-29
申请人: Intel IP Corporation
发明人: Bernd Waidhas , Stephan Stoeckl , Andreas Wolter , Reinhard Mahnkopf , Georg Seidemann , Thomas Wagner , Laurent Millou
IPC分类号: H01L23/06 , H01L23/538 , H01L25/065 , H01L23/00 , H01L21/48 , H01L23/053
摘要: A bent-bridge semiconductive apparatus includes a silicon bridge that is integral to a semiconductive device and the silicon bridge is deflected out of planarity. The silicon bridge may couple two semiconductive devices, all of which are from an integral processed die.
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4.
公开(公告)号:US20190341371A1
公开(公告)日:2019-11-07
申请号:US16515979
申请日:2019-07-18
申请人: Intel IP Corporation
发明人: Bernd Waidhas , Georg Seidemann , Andreas Augustin , Laurent Millou , Andreas Wolter , Reinhard Mahnkopf , Stephan Stoeckl , Thomas Wagner
IPC分类号: H01L25/065 , H01L25/10 , H01L21/48 , H01L23/48 , H01L25/00
摘要: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
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公开(公告)号:US10431545B2
公开(公告)日:2019-10-01
申请号:US15637641
申请日:2017-06-29
申请人: Intel IP Corporation
IPC分类号: H01L23/538 , H01L23/498 , H01L25/065 , G11C16/18
摘要: A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.
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