公开(公告)号：US10150668B2

公开(公告)日：2018-12-11

申请号：US15484765

申请日：2017-04-11

申请人： Intel IP Corporation

发明人： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC分类号： H01L27/14 ,  B81C1/00 ,  B81B7/00

摘要： In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US20170217766A1

公开(公告)日：2017-08-03

申请号：US15484765

申请日：2017-04-11

申请人： Intel IP Corporation

发明人： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC分类号： B81C1/00 ,  B81B7/00

CPC分类号： B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

摘要： In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US20210104359A1

公开(公告)日：2021-04-08

申请号：US17122351

申请日：2020-12-15

申请人： Intel IP Corporation

发明人： Saravana Maruthamuthu ,  Andreas Augustin ,  Andreas Wolter

IPC分类号： H01F27/40 ,  H01G4/30 ,  H01G4/005 ,  H01G4/40 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F27/28

摘要： A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

公开(公告)号：US10122420B2

公开(公告)日：2018-11-06

申请号：US14979185

申请日：2015-12-22

申请人： Intel IP Corporation

发明人： Thorsten Meyer ,  Andreas Augustin ,  Reinhard Golly ,  Peter Baumgartner

IPC分类号： H04B5/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

摘要： Apparatus and methods are provided for wireless communications between integrated circuits or integrated circuit dies of an electronic system. In an example, an apparatus can include a first integrated circuit die including a plurality of integrated circuit devices, a second integrated circuit die including a second plurality of integrated circuit devices, and a conductor device configured to wirelessly receive a signal from the first integrated circuit die, to conduct the signal from a first end of an electrical conductor of the conductor device to a second end of the electrical conductor, and to wirelessly transmit the signal to the second integrated circuit die from the second end of the electrical conductor.

公开(公告)号：US20210273342A1

公开(公告)日：2021-09-02

申请号：US17323278

申请日：2021-05-18

申请人： Intel IP Corporation

发明人： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC分类号： H01Q19/06 ,  H01Q15/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01Q1/48

摘要： Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US20200227388A1

公开(公告)日：2020-07-16

申请号：US16641241

申请日：2017-09-29

申请人： Intel IP Corporation

发明人： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC分类号： H01L25/065 ,  H01L25/00

摘要： A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US20190341371A1

公开(公告)日：2019-11-07

申请号：US16515979

申请日：2019-07-18

申请人： Intel IP Corporation

发明人： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC分类号： H01L25/065 ,  H01L25/10 ,  H01L21/48 ,  H01L23/48 ,  H01L25/00

摘要： A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US09550670B2

公开(公告)日：2017-01-24

申请号：US14731211

申请日：2015-06-04

申请人： Intel IP Corporation

发明人： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

IPC分类号： H01L21/00 ,  B81C1/00 ,  B81B7/00 ,  H01L23/00 ,  H01L21/56

CPC分类号： B81C1/00666 ,  B81B7/0054 ,  B81C1/00261 ,  B81C1/00349 ,  B81C2203/0136 ,  B81C2203/0154 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73277 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.

摘要翻译： 描述了用于集成微机电系统（MEMS）的应力缓冲层。 例如，半导体封装包括具有第一和第二表面的衬底，第二表面具有外部导电触点阵列。 微机电系统（MEMS）部件设置在基板的第一表面上方。 缓冲层设置在MEMS部件上方，缓冲层具有第一杨氏模量。 模具化合物设置在缓冲层上方，模塑料具有高于第一杨氏模量的第二杨氏模量。

公开(公告)号：US20160200566A1

公开(公告)日：2016-07-14

申请号：US14403571

申请日：2013-06-28

申请人： INTEL IP CORPORATION

发明人： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC分类号： B81B7/00 ,  B81C1/00

CPC分类号： B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

摘要： In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

摘要翻译： 在实施例中，封装组件可以包括专用集成电路（ASIC）和具有有源侧和无源侧的微机电系统（MEMS）。 在实施例中，MEMS可以通过一个或多个互连直接耦合到ASIC。 MEMS，ASIC和一个或多个互连可以限定或形成空腔，使得MEMS的有源部分在空腔内。 在一些实施例中，封装组件可以包括通过多个一个或多个互连件直接耦合到ASIC的多个MEMS。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10896780B2

公开(公告)日：2021-01-19

申请号：US15910820

申请日：2018-03-02

申请人： Intel IP Corporation

发明人： Saravana Maruthamuthu ,  Andreas Augustin ,  Andreas Wolter

IPC分类号： H01F27/40 ,  H01G4/30 ,  H01G4/005 ,  H01G4/40 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F27/28 ,  H01L23/532 ,  H03B5/08 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288 ,  H01L21/768

摘要： A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.