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    Components and methods for processing in wireless communication data in presence of format uncertainty
    1.
    发明申请
    Components and methods for processing in wireless communication data in presence of format uncertainty 失效
    在存在格式不确定性的情况下在无线通信数据中处理的组件和方法

    公开(公告)号：US20040165571A1

    公开(公告)日：2004-08-26

    申请号：US10754772

    申请日：2004-01-09

    Applicant: InterDigital Technology Corporation

    Inventor： Alexander Reznik ,  Edward L. Hepler

    IPC: H04J003/24

    CPC classification number: H04L1/1829 ,  H04B1/707 ,  H04L1/0006 ,  H04L1/0025 ,  H04L1/0032 ,  H04L1/0071

    Abstract: Components and method are provided to efficiently process wireless communications data where prior knowledge of the specific format of the communication data is not available. A wireless transmit receive unit (WTRU) is configured for use in a wireless communication system where communication data for selected channels is transmitted in system time frames in formats selected from among a set of predefined formats. The WTRU has a receiver, a memory, a received chip rate processor (RCRP), a format detector and a de-interleaver. The RCRP is preferably configured to despread each wireless signal of spread data received in each time frame using a minimum spreading code or other appropriate key sequence and to store resultant despread data for each respective time frame in the memory. The format detector is preferably configured to determine the number of physical channels and the respective spreading factor for each physical channel for the wireless signal of spread data received in each time frame. The de-interleaver is preferably configured to de-interleave the stored data despread by the RCRP for each respective time frame into the number of physical channels determined by the format detector for the respective time frame.

    Abstract translation: 提供组件和方法以有效地处理无线通信数据，其中通信数据的特定格式的先前知识不可用。 无线发射接收单元（WTRU）被配置为在无线通信系统中使用，其中所选信道的通信数据以系统时间帧的形式从一组预定格式中选出。 WTRU具有接收机，存储器，接收的码片速率处理器（RCRP），格式检测器和解交织器。 优选地，RCRP被配置为使用最小扩展码或其他适当的密钥序列来解扩每个时间帧中接收的扩展数据的每个无线信号，并且将每个相应时间帧的合成解扩数据存储在存储器中。 格式检测器优选地被配置为确定在每个时间帧中接收的扩展数据的无线信号的物理信道的数量和每个物理信道的相应扩展因子。 解交织器优选地被配置为将用于每个相应时间帧的由RCRP解扩的存储的数据解交织成由各个时间帧由格式检测器确定的物理信道的数量。

    Path searcher using reconfigurable correlator sets
    2.
    发明申请
    Path searcher using reconfigurable correlator sets 失效
    路径搜索器使用可重构相关器集

    公开(公告)号：US20040047439A1

    公开(公告)日：2004-03-11

    申请号：US10412475

    申请日：2003-04-11

    Applicant: InterDigital Technology Corporation

    Inventor： John David Kaewell JR. ,  Timothy Berghuis ,  Jan Meyer ,  Peter Bohnhoff ,  Alexander Reznik ,  Edward L. Hepler ,  Michael Koch ,  William C. Hackett ,  David S. Bass ,  Steven Ferrante

    IPC: H04B001/10

    CPC classification number: H04B1/7093 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/709 ,  H04B1/7113 ,  H04B1/7117 ,  H04B1/712 ,  H04B7/0491 ,  H04B2201/7071 ,  H04B2201/70711

    Abstract: A Node-B/base station has a path searcher and at least one antenna for receiving signals from users. The path searcher comprises a set of correlators. Each correlator correlates an inputted user code with an inputted antenna output of the at least one antenna. An antenna controller selectively couples any output of the at least one antenna to an input of each correlator of the set of correlators. A code phase controller selects a user code for input into the set of correlators. Each delay of a series of delays delays the selected user code by a predetermined amount and each correlator of the set of correlators receives a different code phase delay of the selected user code. A sorter and path selector sorts the output energy levels of each correlator of the sets of correlators and produces a path profile for a user based on the sorted output energy levels.

    Abstract translation: 节点B /基站具有路径搜索器和用于从用户接收信号的至少一个天线。 路径搜索器包括一组相关器。 每个相关器将输入的用户代码与至少一个天线的输入的天线输出相关联。 天线控制器选择性地将至少一个天线的任何输出耦合到该组相关器的每个相关器的输入端。 代码相位控制器选择用于输入到该组相关器的用户代码。 一系列延迟的每个延迟将所选择的用户码延迟预定量，并且该组相关器的每个相关器接收所选用户码的不同码相位延迟。 分拣机和路径选择器对相关器组的每个相关器的输出能量进行排序，并且基于排序的输出能级产生用户的路径简档。

    System for generating pseudorandom sequences
    4.
    发明申请
    System for generating pseudorandom sequences 失效
    用于生成伪随机序列的系统

    公开(公告)号：US20020196936A1

    公开(公告)日：2002-12-26

    申请号：US10046601

    申请日：2001-10-23

    Applicant: InterDigital Technology Corporation

    Inventor： Edward L. Hepler

    IPC: H04L009/00

    CPC classification number: G06F1/0255 ,  H04J13/0044 ,  H04J13/12

    Abstract: A system for generating pseudorandom codes using a register which contains an identification of the code tree leg of the desired code and a counter which outputs a successive binary sequence. The output from the counter is bit-by-bit ANDed with the output of the register, and those outputs are XORed together to output a single bit. As the counter is sequenced, each count results in a different bit that is output from the XOR gate, resulting in the desired code.

    Abstract translation: 一种使用包含所需代码的代码树段的标识的寄存器生成伪随机代码的系统和输出连续的二进制序列的计数器。 计数器的输出与寄存器的输出逐位AND，并将这些输出异或并输出一位。 当计数器被排序时，每个计数导致从XOR门输出的不同位，产生所需的代码。

    Pipeline architecture for maximum a posteriori (MAP) decoders
    7.
    发明申请
    Pipeline architecture for maximum a posteriori (MAP) decoders 失效
    最大后验（MAP）解码器的管道架构

    公开(公告)号：US20030066019A1

    公开(公告)日：2003-04-03

    申请号：US10037609

    申请日：2002-01-02

    Applicant: InterDigital Technology Corporation

    Inventor： Edward L. Hepler ,  Michael F. Starsinic

    IPC: G06F007/52 ,  H03M013/03

    CPC classification number: H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

    Abstract: The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

    Abstract translation: 流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。 一旦为解码器的第一滑动窗口计算了前向量度，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。 当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。 用于计算外在值的每个前向量度在相同的时钟边沿从存储器读取，该时钟边沿将新的前向量度写入相同的存储器位置。 虽然该架构是为turbo解码器开发的，但是所有的卷积码都可以使用本发明的MAP算法。

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