公开(公告)号：US20040139140A1

公开(公告)日：2004-07-15

申请号：US10744829

申请日：2003-12-23

Applicant: InterDigital Technology Corporation

Inventor： Peter E. Becker

IPC: G06F007/52

CPC classification number: G06F7/4806 ,  G06F7/535

Abstract: A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication. A second output produces a result of the complex division of the first complex value divided by the second complex value when the circuit is performing the complex division and complex multiplication of the fifth complex value by the sixth complex value when performing the dual complex multiplication.

Abstract translation: 电路能够执行复杂的分割和双重复数乘法。 复分割涉及将第一复数值除以第二复数值，并且双复数乘法涉及将第三复数值乘以第四复数值和第五复数值乘以第六复数值。 该电路包括第一输入，其被配置为当电路执行复分频时接收第一和第二复数值，以及当电路执行双复数乘法时，第三和第四复数值。 第二输入被配置为当执行复数除法时接收第二复数值，并且当执行双复数乘法时被配置为接收第二复数值。 当电路执行双复数乘法时，第一输出产生第三和第四复数值的复相乘的结果。 当执行双复数乘法时，当电路执行复分数和第五复数乘以第六复数值时，第二输出产生第一复数值除以第二复数值的复分解的结果。

公开(公告)号：US20030091007A1

公开(公告)日：2003-05-15

申请号：US10172113

申请日：2002-06-14

Applicant: InterDigital Technology Corporation

Inventor： Peter E. Becker ,  Stephan Shane Supplee

IPC: H04B007/216

CPC classification number: G06F17/16 ,  G06F17/12 ,  H04B1/7105 ,  H04B1/71055

Abstract: A user equipment or base station recovers data from a plurality of data signals received as a received vector. The user equipment determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The user equipment or base station comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.

Abstract translation: 用户设备或基站从作为接收向量接收的多个数据信号中恢复数据。 用户设备通过确定N乘N矩阵的Cholesky因子并使用所确定的Cholesky因子进行前向和后向替换来确定接收到的数据信号的数据来确定接收向量的数据。 用户设备或基站包括至多N个标量处理元件的阵列。 该阵列具有用于从N×N矩阵和接收向量接收元素的输入。 每个标量处理元素用于确定Cholesky因子并执行向前和向后替换。 阵列输出接收矢量的数据。

公开(公告)号：US20030225809A1

公开(公告)日：2003-12-04

申请号：US10322160

申请日：2002-12-18

Applicant: InterDigital Technology Corporation

Inventor： Peter E. Becker

IPC: G06F007/52

CPC classification number: G06F7/4806 ,  G06F7/535

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

Abstract translation: 电路执行复杂划分和双重复数乘法。 该电路具有多个乘法器。 多个乘法器中的每一个在复数除法和双复数乘法中都被使用。 该电路还具有能够增减的多个部件。 在复分频期间使用每个加法和减法分量，并且双复数乘法和作为加法器的操作和在执行复分频和双复数乘法之间的减法器之间切换。 电路的优选潜在用途在用户设备或基站的接收机中。 该电路用于基于快速傅里叶变换（FFT）的信道估计或基于FFT的数据检测。