公开(公告)号：US20040174854A1

公开(公告)日：2004-09-09

申请号：US10725808

申请日：2003-12-02

Applicant: InterDigital Technology Corporation

Inventor： Stephan Shane Supplee ,  Chayil S. Timmerman ,  Ryan Samuel Buchert ,  Peter Edward Becker ,  Tonino Nasuti ,  Robert A. DiFazio ,  John W. Haim

IPC: H04B007/216

CPC classification number: H04B1/71052 ,  H04B2201/70707

Abstract: Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.

Abstract translation: 优化多用户检测（MUD）性能，以消除处理过程中冗余电源的使用。 提供了一种过度建立的A矩阵，即系统响应矩阵。 过量的A矩阵使用所有可能的代码，例如由盲代码检测（BCD）提供的候选代码表（CCL）中标识的所有代码。 过量的A矩阵被传递给仅提取实际已经接收的代码所需的行或列的MUD，从而不需要重新计算与实际接收的代码不对应的白化匹配滤波器（WMF）输出。

公开(公告)号：US20040230632A1

公开(公告)日：2004-11-18

申请号：US10670062

申请日：2003-09-24

Applicant: InterDigital Technology Corporation

Inventor： Ryan Samuel Buchert ,  Chayil S. Timmerman ,  Stephan Shane Supplee

IPC: G06F007/52

CPC classification number: G06F5/015 ,  G06F17/16

Abstract: A method and system for performing many different types if algorithms utilizes a single mathematical engine such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register, at least one selectively controlled memory, and a plurality of processing elements. The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.

Abstract translation: 用于执行许多不同类型的算法的方法和系统利用单个数学引擎，使得数学引擎能够对所有算法使用相同的乘法器。 数学引擎包括选择性控制的并行输出寄存器，至少一个选择性控制的存储器和多个处理元件。 根据要执行的算法，选择性地控制输出寄存器，存储器和处理元件。

公开(公告)号：US20030091007A1

公开(公告)日：2003-05-15

申请号：US10172113

申请日：2002-06-14

Applicant: InterDigital Technology Corporation

Inventor： Peter E. Becker ,  Stephan Shane Supplee

IPC: H04B007/216

CPC classification number: G06F17/16 ,  G06F17/12 ,  H04B1/7105 ,  H04B1/71055

Abstract: A user equipment or base station recovers data from a plurality of data signals received as a received vector. The user equipment determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The user equipment or base station comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.

Abstract translation: 用户设备或基站从作为接收向量接收的多个数据信号中恢复数据。 用户设备通过确定N乘N矩阵的Cholesky因子并使用所确定的Cholesky因子进行前向和后向替换来确定接收到的数据信号的数据来确定接收向量的数据。 用户设备或基站包括至多N个标量处理元件的阵列。 该阵列具有用于从N×N矩阵和接收向量接收元素的输入。 每个标量处理元素用于确定Cholesky因子并执行向前和向后替换。 阵列输出接收矢量的数据。