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公开(公告)号：US11474821B1
公开(公告)日：2022-10-18
申请号：US17318252
申请日：2021-05-12
发明人： Amir Turi , Avraham Ayzenfeld , Gilad Shimon Merran , Yanai Danan , Amit Shay , Yossi Shapira , Yair Fried , Oren Ben Gigi , Omri Rafaeli
IPC分类号： G06F9/38
摘要： In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.
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公开(公告)号：US10649777B2
公开(公告)日：2020-05-12
申请号：US15978245
申请日：2018-05-14
发明人： Yossi Shapira , Eyal Naor , Gregory Miaskovsky , Yair Fried
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30
摘要： Prefetching data by determining that a first set of instructions that is processed by a computer processor indicates that a second set of instructions includes multiple iteration groups, where each of the iteration groups includes one or more loop-unrolled instructions, monitoring the second set of instructions as the second set of instructions is processed by the computer processor after the first set of instructions is processed by the computer processor, mapping a corresponding one of the loop-unrolled instructions in each of the iteration groups of the second set of instructions to a stride-tracking record that is shared by the corresponding loop-unrolled instructions, and prefetching data into a cache memory of the computer processor based on the stride-tracking record.
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公开(公告)号：US20190370186A1
公开(公告)日：2019-12-05
申请号：US15996646
申请日：2018-06-04
IPC分类号： G06F12/123 , G06F12/0817 , G06F12/084 , G06F12/0811 , G06F12/02
摘要： A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.
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公开(公告)号：US11157281B2
公开(公告)日：2021-10-26
申请号：US15988070
申请日：2018-05-24
发明人： Eyal Naor , Yossi Shapira , Yair Fried , Amir Turi
IPC分类号： G06F9/345 , G06F12/0862
摘要： Prefetching data by detecting a predefined pattern of register activity of a computer processor by detecting when data, at a memory address pointed to by the sum of an offset value and the contents of a register of the processor during an instruction cycle of the processor, is loaded into the register as a result of processing an instruction, detecting the pattern by detecting when data, at a memory address pointed to by the sum of the offset value and the contents of the register during at least one subsequent instruction cycle, is loaded into the register as a result of again processing the instruction, and prefetching data, into a cache memory of the processor, from a current prefetching memory address, where data, at a memory address pointed to by the sum of the offset value and the contents of the register, is used as the current prefetching memory address.
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公开(公告)号：US11080199B2
公开(公告)日：2021-08-03
申请号：US16295117
申请日：2019-03-07
IPC分类号： G06F12/0875 , G06F9/50 , G06F9/30 , G06F12/12
摘要： Embodiments of the inventions are directed towards a computer-implemented methods and systems for determining an oldest logical memory address. The method includes creating an M number of miss request registers and an N number of stations in a load/store unit of the processor. In response to load requests from target instructions, a processor detects each L1 cache miss. The processor stores data related to each L1 cache miss in a respective miss request register. The data includes an age of each L1 cache miss and a portion of a logical memory address of the requested load. The processor stores the entire logical memory addresses of the requested loads in respective stations based on an age of the load requests. The processor transmits the oldest logical memory address that is stored at the stations.
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公开(公告)号：US10572387B2
公开(公告)日：2020-02-25
申请号：US15867989
申请日：2018-01-11
发明人： Dwifuzi Coe , Yair Fried , Martin Recktenwald , Yossi Shapira
IPC分类号： G06F12/0891 , G06F12/0831 , G06F12/128
摘要： A memory access control includes a tracker configured to receive cache invalidate (XI) commands from the memory controller and to provide responses to the memory controller and an address storage element in the tracker that stores an address to be locked by one of the processing units. The system also includes a lock required, a cache invalidate (XI) tracker bit, a set input that upon receipt of a set command sets the lock required bit when a first condition is met, a first reset input that resets the lock required bit upon receipt of a reset command; and a second reset input that resets the XI tracker bit. The tracker rejects incoming XI commands from the memory controller when the lock required bit is set, allows incoming XI commands when the lock bit is not set and sets the XI tracker bit when a first incoming XI command is received.
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公开(公告)号：US20200285583A1
公开(公告)日：2020-09-10
申请号：US16295117
申请日：2019-03-07
IPC分类号： G06F12/0875 , G06F12/12 , G06F9/30 , G06F9/50
摘要： Embodiments of the inventions are directed towards a computer-implemented methods and systems for determining an oldest logical memory address. The method includes creating an M number of miss request registers and an N number of stations in a load/store unit of the processor. In response to load requests from target instructions, a processor detects each L1 cache miss. The processor stores data related to each L1 cache miss in a respective miss request register. The data includes an age of each L1 cache miss and a portion of a logical memory address of the requested load. The processor stores the entire logical memory addresses of the requested loads in respective stations based on an age of the load requests. The processor transmits the oldest logical memory address that is stored at the stations.
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公开(公告)号：US10528482B2
公开(公告)日：2020-01-07
申请号：US15996646
申请日：2018-06-04
IPC分类号： G06F12/12 , G06F12/123 , G06F12/0817 , G06F12/0811 , G06F12/02 , G06F12/084
摘要： A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.
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公开(公告)号：US12099845B2
公开(公告)日：2024-09-24
申请号：US17807243
申请日：2022-06-16
IPC分类号： G06F9/38 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3808 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3856 , G06F12/0875 , G06F2212/452
摘要： In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.
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公开(公告)号：US20230409331A1
公开(公告)日：2023-12-21
申请号：US17807243
申请日：2022-06-16
IPC分类号： G06F9/38 , G06F12/0875
CPC分类号： G06F9/3808 , G06F9/3855 , G06F12/0875 , G06F2212/452
摘要： In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.
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