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    VARIABLE FREQUENCY OSCILLATOR WITH SPECIALIZED INVERTER STAGES
    1.
    发明申请
    VARIABLE FREQUENCY OSCILLATOR WITH SPECIALIZED INVERTER STAGES 有权
    具有专用逆变器级的可变频率振荡器

    公开(公告)号：US20150171790A1

    公开(公告)日：2015-06-18

    申请号：US14109364

    申请日：2013-12-17

    Applicant: International Business Machines Corporation

    Inventor： Andrew D. Davies ,  Joel T. Ficke ,  David M. Friend ,  Grant P. Kesselring ,  James D. Strom

    IPC: H03B5/12

    CPC classification number: H03B5/124 ,  H03K3/0315 ,  H03K3/354

    Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

    Abstract translation: 可变频率振荡器装置包括：第一反相器级，其被设计成通过使用电流源对电容器进行充电和放电来反转输入信号以产生锯齿波信号，所述电流源各自提供响应于控制信号的相应量的电流， 衰减信号。 第二反相器级被设计为从第一反相器级的锯齿波信号产生第一反相信号。 第三反相器级被设计为从第一反相信号产生第二反相信号，并且基于控制信号抑制第一反相信号的信号转变速率。

    IMPLEMENTING CLOCK RECEIVER WITH LOW JITTER AND ENHANCED DUTY CYCLE
    2.
    发明申请
    IMPLEMENTING CLOCK RECEIVER WITH LOW JITTER AND ENHANCED DUTY CYCLE 有权
    实现低抖动和增强占空比的时钟接收器

    公开(公告)号：US20160191023A1

    公开(公告)日：2016-06-30

    申请号：US14583963

    申请日：2014-12-29

    Applicant: International Business Machines Corporation

    Inventor： Andrew D. Davies ,  Grant P. Kesselring ,  Christopher W. Steffen ,  James D. Strom

    IPC: H03K3/017 ,  H03L7/10

    CPC classification number: H03K3/017 ,  H03K3/353 ,  H03K3/356104 ,  H03K5/1252 ,  H03L7/10

    Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current minors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

    Abstract translation: 一种用于实现低抖动和增强占空比的方法和时钟接收器电路，以及设置有被摄体电路的设计结构。 时钟接收器电路接受单端互补金属氧化物半导体（CMOS）和差分时钟信号。 时钟接收器电路包括耦合到差分对的输入电路，其偏置参考时钟并允许单端或差分时钟信号。 差分对使用多个当前未成年人来切换输入信号的极性以实现增强的抖动性能，以及用于保持信号对称性的交叉耦合逆变器。

    VOLTAGE-CONTROLLED OSCILLATOR WITH CENTERTAP BIAS
    3.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATOR WITH CENTERTAP BIAS 有权

    公开(公告)号：US20220345085A1

    公开(公告)日：2022-10-27

    申请号：US17239862

    申请日：2021-04-26

    Applicant: International Business Machines Corporation

    Inventor： James Strom ,  Herschel Akiba Ainspan ,  Andrew D. Davies ,  John Borkenhagen

    IPC: H03B5/12

    Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

    Voltage-controlled oscillator with centertap bias
    5.
    发明授权
    Voltage-controlled oscillator with centertap bias 有权

    公开(公告)号：US11496094B1

    公开(公告)日：2022-11-08

    申请号：US17239862

    申请日：2021-04-26

    Applicant: International Business Machines Corporation

    Inventor： James Strom ,  Herschel Akiba Ainspan ,  Andrew D. Davies ,  John Borkenhagen

    IPC: H03B5/12

    Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

    Implementing clock receiver with low jitter and enhanced duty cycle
    7.
    发明授权
    Implementing clock receiver with low jitter and enhanced duty cycle 有权
    实现具有低抖动和增强占空比的时钟接收器

    公开(公告)号：US09438209B2

    公开(公告)日：2016-09-06

    申请号：US14583963

    申请日：2014-12-29

    Applicant: International Business Machines Corporation

    Inventor： Andrew D. Davies ,  Grant P. Kesselring ,  Christopher W. Steffen ,  James D. Strom

    IPC: H03K5/04 ,  H03K3/017 ,  H03L7/10

    CPC classification number: H03K3/017 ,  H03K3/353 ,  H03K3/356104 ,  H03K5/1252 ,  H03L7/10

    Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

    Abstract translation: 一种用于实现低抖动和增强占空比的方法和时钟接收器电路，以及设置有被摄体电路的设计结构。 时钟接收器电路接受单端互补金属氧化物半导体（CMOS）和差分时钟信号。 时钟接收器电路包括耦合到差分对的输入电路，其偏置参考时钟并允许单端或差分时钟信号。 差分对使用多个电流镜来切换输入信号的极性以实现增强的抖动性能，以及用于保持信号对称性的交叉耦合反相器。

    Variable frequency oscillator with specialized inverter stages
    8.
    发明授权
    Variable frequency oscillator with specialized inverter stages 有权
    具有专门变频器级的变频振荡器

    公开(公告)号：US09059660B1

    公开(公告)日：2015-06-16

    申请号：US14109364

    申请日：2013-12-17

    Applicant: International Business Machines Corporation

    Inventor： Andrew D. Davies ,  Joel T. Ficke ,  David M. Friend ,  Grant P. Kesselring ,  James D. Strom

    IPC: H03B5/02 ,  H03B5/12

    CPC classification number: H03B5/124 ,  H03K3/0315 ,  H03K3/354

    Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

    Abstract translation: 可变频率振荡器装置包括：第一反相器级，其被设计成通过使用电流源对电容器进行充电和放电来反转输入信号以产生锯齿波信号，所述电流源各自提供响应于控制信号的相应量的电流， 衰减信号。 第二反相器级被设计为从第一反相器级的锯齿波信号产生第一反相信号。 第三反相器级被设计为从第一反相信号产生第二反相信号，并且基于控制信号抑制第一反相信号的信号转变速率。

    High frequency AC coupled self-biased divider
    9.
    发明授权
    High frequency AC coupled self-biased divider 有权

    公开(公告)号：US11750180B2

    公开(公告)日：2023-09-05

    申请号：US17469402

    申请日：2021-09-08

    Applicant: International Business Machines Corporation

    Inventor： James Strom ,  Grant P. Kesselring ,  Andrew D. Davies ,  Ann Chen Wu

    IPC: H03K5/01 ,  G06F1/08

    CPC classification number: H03K5/01 ,  G06F1/08

    Abstract: Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

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