公开(公告)号：US12111684B2

公开(公告)日：2024-10-08

申请号：US18455101

申请日：2023-08-24

申请人： International Business Machines Corporation

发明人： Douglas J. Malone ,  Andreas H. A. Arp ,  Franklin M. Baez ,  Daniel M. Dreps ,  Jason Lee Frankel ,  Chad Andrew Marquart ,  Ching Lung Tong ,  Lily Jielu Zhang

IPC分类号： G06F1/12 ,  G06F1/08 ,  H03L7/085

CPC分类号： G06F1/12 ,  G06F1/08 ,  H03L7/085

摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

公开(公告)号：US20230085155A1

公开(公告)日：2023-03-16

申请号：US17471442

申请日：2021-09-10

申请人： International Business Machines Corporation

发明人： Douglas J. Malone ,  Andreas H. A. Arp ,  Franklin M. Baez ,  Daniel M. Dreps ,  Jason Lee Frankel ,  Chad Andrew Marquart ,  Ching Lung Tong ,  Lily Jielu Zhang

IPC分类号： G06F1/12 ,  G06F1/08 ,  H03L7/085

摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

公开(公告)号：US20230393610A1

公开(公告)日：2023-12-07

申请号：US18455101

申请日：2023-08-24

申请人： International Business Machines Corporation

发明人： Douglas J. Malone ,  Andreas H. A. Arp ,  Franklin M. Baez ,  Daniel M. Dreps ,  Jason Lee Frankel ,  Chad Andrew Marquart ,  Ching Lung Tong ,  Lily Jielu Zhang

IPC分类号： G06F1/12 ,  H03L7/085 ,  G06F1/08

CPC分类号： G06F1/12 ,  H03L7/085 ,  G06F1/08

摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

公开(公告)号：US11775004B2

公开(公告)日：2023-10-03

申请号：US17471442

申请日：2021-09-10

申请人： International Business Machines Corporation

发明人： Douglas J. Malone ,  Andreas H. A. Arp ,  Franklin M. Baez ,  Daniel M. Dreps ,  Jason Lee Frankel ,  Chad Andrew Marquart ,  Ching Lung Tong ,  Lily Jielu Zhang

IPC分类号： G06F1/08 ,  G06F1/12 ,  H03L7/085

CPC分类号： G06F1/12 ,  G06F1/08 ,  H03L7/085

摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.