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1.发明授权公开(公告)号：US12111684B2
公开(公告)日：2024-10-08
申请号：US18455101
申请日：2023-08-24
发明人： Douglas J. Malone , Andreas H. A. Arp , Franklin M. Baez , Daniel M. Dreps , Jason Lee Frankel , Chad Andrew Marquart , Ching Lung Tong , Lily Jielu Zhang
摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
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公开(公告)号：US10423751B2
公开(公告)日：2019-09-24
申请号：US15719698
申请日：2017-09-29
IPC分类号： G06F17/50
摘要： Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.
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3.发明公开公开(公告)号：US20230393610A1
公开(公告)日：2023-12-07
申请号：US18455101
申请日：2023-08-24
发明人： Douglas J. Malone , Andreas H. A. Arp , Franklin M. Baez , Daniel M. Dreps , Jason Lee Frankel , Chad Andrew Marquart , Ching Lung Tong , Lily Jielu Zhang
摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
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4.发明授权公开(公告)号：US11775004B2
公开(公告)日：2023-10-03
申请号：US17471442
申请日：2021-09-10
发明人： Douglas J. Malone , Andreas H. A. Arp , Franklin M. Baez , Daniel M. Dreps , Jason Lee Frankel , Chad Andrew Marquart , Ching Lung Tong , Lily Jielu Zhang
摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
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公开(公告)号：US10756031B1
公开(公告)日：2020-08-25
申请号：US16409321
申请日：2019-05-10
发明人： Charles L. Arvin , Franklin M. Baez , Brian W. Quinlan , Charles L. Reynolds , Krishna R. Tunga , Thomas Weiss
IPC分类号： H01L23/34 , H01L23/64 , H01L49/02 , H01L23/04 , H01L23/522
摘要： An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.
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6.发明申请公开(公告)号：US20230085155A1
公开(公告)日：2023-03-16
申请号：US17471442
申请日：2021-09-10
发明人： Douglas J. Malone , Andreas H. A. Arp , Franklin M. Baez , Daniel M. Dreps , Jason Lee Frankel , Chad Andrew Marquart , Ching Lung Tong , Lily Jielu Zhang
摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
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公开(公告)号：US10949600B2
公开(公告)日：2021-03-16
申请号：US16539120
申请日：2019-08-13
IPC分类号： G06F30/398 , G06F30/392 , G06F113/18
摘要： Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.
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公开(公告)号：US20200075468A1
公开(公告)日：2020-03-05
申请号：US16120782
申请日：2018-09-04
IPC分类号： H01L23/498 , H01L25/16 , H01L49/02
摘要： An integrated circuit (IC) chip carrier includes one or more internal metal planes. A dedicated metal plane (DMP) may be formed upon a metal plane dielectric layer. The metal plane dielectric layer may be formed upon a first dielectric layer that is formed upon an IC chip carrier core. The DMP may be formed of the same or different material relative to the material of the wires of the IC chip carrier. The side surfaces of the DMP may be coplanar with associated side surfaces of the IC chip carrier. The DMP may transfer heat from the IC chip horizontally to its side surfaces. A decoupling capacitor is externally connected to the IC chip carrier and is electrically connected to the DMP. By connecting the decoupling capacitor to the DMP, the decoupling capacitor may further reduce inductance and noise within the IC chip system.
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公开(公告)号：US20190102505A1
公开(公告)日：2019-04-04
申请号：US15719698
申请日：2017-09-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/40
摘要： Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.
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