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公开(公告)号:US10970224B2
公开(公告)日:2021-04-06
申请号:US16456000
申请日:2019-06-28
发明人: Elpida Tzortzatos , Steven M. Partlow , Scott B. Compton , Christine Michele Yost , Charles F. Webb , Christian Jacobi
IPC分类号: G06F12/10 , G06F12/0891 , G06F12/1027 , G06F12/109
摘要: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.
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2.
公开(公告)号:US11593275B2
公开(公告)日:2023-02-28
申请号:US17335232
申请日:2021-06-01
发明人: Christine Michele Yost , Elpida Tzortzatos , Bruce Conrad Giamei , Timothy Slegel , Christian Borntraeger , Damian Osisek , Lisa Cranton Heller , Ute Gaertner
IPC分类号: G06F12/1027 , G06F12/02 , G06F9/38 , G06F9/30 , G06F12/0831
摘要: Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.
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3.
公开(公告)号:US11074195B2
公开(公告)日:2021-07-27
申请号:US16456006
申请日:2019-06-28
发明人: Elpida Tzortzatos , Steven M. Partlow , Scott B. Compton , Christine Michele Yost , Peter Jeremy Relson
IPC分类号: G06F12/10 , G06F12/109
摘要: A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.
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