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公开(公告)号：US10540183B2
公开(公告)日：2020-01-21
申请号：US15798887
申请日：2017-10-31
发明人： Khary J. Alexander , Fadi Y. Busaba , Brian W. Curran , David S. Hutton , Edward T. Malley , Brian R. Prasky , John G. Rell, Jr.
摘要： As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.
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公开(公告)号：US20160210153A1
公开(公告)日：2016-07-21
申请号：US14599693
申请日：2015-01-19
发明人： Khary J. Alexander , Fadi Y. Busaba , Brian W. Curran , David S. Hutton , Edward T. Malley , Brian R. Prasky , John G. Rell, JR.
CPC分类号： G06F9/3822 , G06F9/30032 , G06F9/3005 , G06F9/30145 , G06F9/3016 , G06F9/30181 , G06F9/322 , G06F9/3867
摘要： As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.
摘要翻译： 如本文所公开的，由处理器执行的用于加速指令执行的方法包括检索包括寄存器参考和对目标指令的引用的执行指令，检索目标指令，使用指令流水线解码执行指令，解码目标指令 使用指令流水线，将寄存器引用与目标指令相关联，并使用寄存器引用执行目标指令作为源操作数修改器。 指令流水线被配置为使得其允许目标指令继续处理而不等待寄存器引用被解决。 引用寄存器的内容可以在指令流水线的后期检索，并且可以修改和执行目标指令。 本文还公开了与所述方法对应的装置。
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公开(公告)号：US20160210150A1
公开(公告)日：2016-07-21
申请号：US14980476
申请日：2015-12-28
发明人： Khary J. Alexander , Fadi Y. Busaba , Brian W. Curran , David S. Hutton , Edward T. Malley , Brian R. Prasky , John G. Rell, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3822 , G06F9/30032 , G06F9/3005 , G06F9/30145 , G06F9/3016 , G06F9/30181 , G06F9/322 , G06F9/3867
摘要： As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.
摘要翻译： 如本文所公开的，由处理器执行的用于加速指令执行的方法包括检索包括寄存器参考和对目标指令的引用的执行指令，检索目标指令，使用指令流水线解码执行指令，解码目标指令 使用指令流水线，将寄存器引用与目标指令相关联，并使用寄存器引用执行目标指令作为源操作数修改器。 指令流水线被配置为使得其允许目标指令继续处理而不等待寄存器引用被解决。 引用寄存器的内容可以在指令流水线的后期检索，并且可以修改和执行目标指令。 本文还公开了与所述方法对应的装置。
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公开(公告)号：US11303456B2
公开(公告)日：2022-04-12
申请号：US16276730
申请日：2019-02-15
摘要： A single architected instruction to produce a signature for a message is obtained. The instruction is executed, and the executing includes determining a sign function of a plurality of sign functions supported by the instruction to be performed. Input for the instruction is obtained, and the input includes a message and a cryptographic key. A signature is produced based on the sign function to be performed and the input. The signature is to be used to verify the message.
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公开(公告)号：US11175923B2
公开(公告)日：2021-11-16
申请号：US15431240
申请日：2017-02-13
发明人： Gregory W. Alexander , James J. Bonanno , Adam B. Collura , Bruce C. Giamei , Christian Jacobi , Jang-Soo Lee , Edward T. Malley , Lawrence J. Powell, Jr. , Anthony Saporito
IPC分类号： G06F9/38
摘要： A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.
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公开(公告)号：US20190018676A1
公开(公告)日：2019-01-17
申请号：US15651558
申请日：2017-07-17
发明人： Gregory W. Alexander , David S. Hutton , Christian Jacobi , Edward T. Malley , Anthony Saporito
摘要： Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.
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公开(公告)号：US09389865B1
公开(公告)日：2016-07-12
申请号：US14980476
申请日：2015-12-28
发明人： Khary J. Alexander , Fadi Y. Busaba , Brian W. Curran , David S. Hutton , Edward T. Malley , Brian R. Prasky , John G. Rell, Jr.
CPC分类号： G06F9/3822 , G06F9/30032 , G06F9/3005 , G06F9/30145 , G06F9/3016 , G06F9/30181 , G06F9/322 , G06F9/3867
摘要： As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.
摘要翻译： 如本文所公开的，由处理器执行的用于加速指令执行的方法包括检索包括寄存器参考和对目标指令的引用的执行指令，检索目标指令，使用指令流水线解码执行指令，解码目标指令 使用指令流水线，将寄存器引用与目标指令相关联，并使用寄存器引用执行目标指令作为源操作数修改器。 指令流水线被配置为使得其允许目标指令继续处理而不等待寄存器引用被解决。 引用寄存器的内容可以在指令流水线的后期检索，并且可以修改和执行目标指令。 本文还公开了与所述方法对应的装置。
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公开(公告)号：US10599431B2
公开(公告)日：2020-03-24
申请号：US15651558
申请日：2017-07-17
发明人： Gregory W. Alexander , David S. Hutton , Christian Jacobi , Edward T. Malley , Anthony Saporito
摘要： Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.
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公开(公告)号：US20190129717A1
公开(公告)日：2019-05-02
申请号：US15800321
申请日：2017-11-01
发明人： Gregory W. Alexander , David S. Hutton , Christian Jacobi , Edward T. Malley , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/3013 , G06F9/3016 , G06F9/30181 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Embodiments of the invention are directed to methods for handling scratch registers in a processor. The method includes receiving a cracked instruction in an instruction dispatch unit of the processor. The method further includes decoding the cracked instruction into a group of micro-operations. Based on a determination that the instruction group uses a scratch register, determining if the scratch register is used in other groups of micro-operations. Based on a determination that the scratch register is not used in other instruction groups, allocating a physical register for use as the scratch register without creating a mapper entry for the scratch register.
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公开(公告)号：US09875107B2
公开(公告)日：2018-01-23
申请号：US14599693
申请日：2015-01-19
发明人： Khary J. Alexander , Fadi Y. Busaba , Brian W. Curran , David S. Hutton , Edward T. Malley , Brian R. Prasky , John G. Rell, Jr.
CPC分类号： G06F9/3822 , G06F9/30032 , G06F9/3005 , G06F9/30145 , G06F9/3016 , G06F9/30181 , G06F9/322 , G06F9/3867
摘要： As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.
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