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18 条记录 (耗时 0.021 秒)

    Most favored branch issue
    2.
    发明授权
    Most favored branch issue 有权

    公开(公告)号：US10831492B2

    公开(公告)日：2020-11-10

    申请号：US16028177

    申请日：2018-07-05

    申请人： International Business Machines Corporation

    发明人： Salma Ayub ,  Glenn O. Kincaid ,  Christopher M. Mueller ,  Dung Q. Nguyen ,  Eula Faye Abalos Tolentino ,  Albert J. Van Norstrand, Jr. ,  Kenneth L. Ward

    IPC分类号： G06F9/38 ,  G06F9/30

    摘要： Systems, methods, and computer program products are disclosed that control issuing branch instructions in a simultaneous multi-threading (SMT) system. An embodiment system includes an SMT processor circuit that receives, from one of a plurality of threads, a branch instruction having a favor bit. The SMT processor circuit schedules the branch instruction to issue, relative to branch instructions received from other threads in the plurality of threads, based on the favor bit. When the favor bit has a first value, the branch instruction is scheduled to have a higher priority to issue before the branch instructions received from other threads in the plurality of threads. When the favor bit has a second value, the branch instruction is scheduled to issue based an age of the branch instruction relative to respective ages of the branch instructions received from other threads in the plurality of threads.

    Completion mechanism for a microprocessor instruction completion table
    4.
    发明授权
    Completion mechanism for a microprocessor instruction completion table 有权

    公开(公告)号：US10725786B2

    公开(公告)日：2020-07-28

    申请号：US16109952

    申请日：2018-08-23

    申请人： International Business Machines Corporation

    发明人： Kenneth L. Ward ,  Susan E. Eisen ,  Dung Q. Nguyen ,  Glenn O. Kincaid ,  Joe Lee ,  Deepak K. Singh

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/34

    摘要： Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.

    Finish exception handling of an instruction completion table
    7.
    发明授权
    Finish exception handling of an instruction completion table 有权

    公开(公告)号：US11086630B1

    公开(公告)日：2021-08-10

    申请号：US16802679

    申请日：2020-02-27

    申请人： International Business Machines Corporation

    发明人： Kenneth L. Ward ,  Susan Eisen ,  Christopher M. Mueller ,  Glenn O. Kincaid ,  Dhivya Jeganathan

    IPC分类号： G06F9/30 ,  G06F9/38

    摘要： A computer system includes a dispatch stage configured to dispatch a plurality of instructions in a program order, and an issue stage configured to issue at least one instruction among the plurality of instructions. The computer system further includes an execution stage configured to execute the at least one instruction to generate a finish report and to determine the at least one instruction is one of an exception-free instruction or an exception instruction. In response to determining the exception-free instruction, a first finish report associated with the exception-free instruction is output to a completion stage. In response to determining the exception instruction, a second finish report associated with the exception instruction is output to an exception unit so as to halt output of the second finish report to the completion stage.

    Variable latency flush filtering
    8.
    发明授权
    Variable latency flush filtering 有权

    公开(公告)号：US10552162B2

    公开(公告)日：2020-02-04

    申请号：US15876273

    申请日：2018-01-22

    申请人： International Business Machines Corporation

    发明人： Glenn O. Kincaid ,  David S. Levitan ,  Albert J. Van Norstrand, Jr.

    IPC分类号： G06F9/38 ,  G06F9/30

    摘要： Variable latency flush filtering including receiving a first flush instruction tag (ITAG) and a second flush ITAG, wherein the first flush ITAG and the second flush ITAG are instructions to invalidate internal operation results after an internal operation identified by the first flush ITAG and the second flush ITAG; determining that the second flush ITAG is before the first flush ITAG by comparing the first flush ITAG and the second flush ITAG; determining that the first flush ITAG requires adjustment; and delaying the flush to a subsequent cycle in response to determining that the second flush ITAG is before the first flush ITAG and determining that the first flush ITAG requires adjustment.

    Sleeping and waking-up address translation that conflicts with translation level of active page table walks
    9.
    发明授权
    Sleeping and waking-up address translation that conflicts with translation level of active page table walks 有权

    公开(公告)号：US11636043B2

    公开(公告)日：2023-04-25

    申请号：US17461919

    申请日：2021-08-30

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Charles D. Wait ,  Jake Truelove ,  David Campbell ,  Jody Joyner ,  Jon K. Kriegel ,  Glenn O. Kincaid

    IPC分类号： G06F12/1009

    摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

    SLEEP / WAKE-UP PERFORMANCE ENHANCING FOR SIMULTANEOUS ADDRESS TRANSLATION TABLE WALKS
    10.
    发明申请
    SLEEP / WAKE-UP PERFORMANCE ENHANCING FOR SIMULTANEOUS ADDRESS TRANSLATION TABLE WALKS 有权

    公开(公告)号：US20230062909A1

    公开(公告)日：2023-03-02

    申请号：US17461919

    申请日：2021-08-30

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Charles D. Wait ,  Jake Truelove ,  David Campbell ,  Jody Joyner ,  Jon K. Kriegel ,  Glenn O. Kincaid

    IPC分类号： G06F12/1009

    摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.