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公开(公告)号：US11636043B2
公开(公告)日：2023-04-25
申请号：US17461919
申请日：2021-08-30
发明人： Charles D. Wait , Jake Truelove , David Campbell , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009
摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.
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公开(公告)号：US20230062909A1
公开(公告)日：2023-03-02
申请号：US17461919
申请日：2021-08-30
发明人： Charles D. Wait , Jake Truelove , David Campbell , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009
摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.
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公开(公告)号：US20220292028A1
公开(公告)日：2022-09-15
申请号：US17199315
申请日：2021-03-11
发明人： Charles D. Wait , David Campbell , Jake Truelove , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009 , G06F12/1045 , G06F12/0864 , G06F12/0882
摘要： A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.
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公开(公告)号：US10042417B2
公开(公告)日：2018-08-07
申请号：US15202556
申请日：2016-07-05
摘要： A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
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公开(公告)号：US20130191432A1
公开(公告)日：2013-07-25
申请号：US13793240
申请日：2013-03-11
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30189 , G06F9/3861 , G06F2207/382 , G06F2207/3828
摘要： A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value.
摘要翻译： 浮点执行单元能够选择性地重新排列浮点值中的有效位的子集，以用作附加指数位以动态地提供用于浮点计算的扩展范围。 浮点操作数的有效位域可以被认为包括第一和第二部分，其中第一部分能够与第二部分连接以表示浮点值的有效位数，或者提供扩展的范围，被连接 与浮点运算数的指数字段表示浮点值的指数。
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公开(公告)号：US20220309000A1
公开(公告)日：2022-09-29
申请号：US17215287
申请日：2021-03-29
发明人： David Campbell , George W. Rohrbaugh, III , Jake Truelove , Jon K. Kriegel , Charles D. Wait , Jody Joyner
IPC分类号： G06F12/0862 , G06F12/0864 , G06F12/1045 , G06F12/02
摘要： A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.
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公开(公告)号：US11422947B2
公开(公告)日：2022-08-23
申请号：US16991075
申请日：2020-08-12
发明人： David Campbell , Jake Truelove , Charles D. Wait , Jon K. Kriegel
IPC分类号： G06F12/1045 , G06F12/1027 , G06F12/1009
摘要： A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.
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公开(公告)号：US10067556B2
公开(公告)日：2018-09-04
申请号：US14841016
申请日：2015-08-31
摘要： A method maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
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公开(公告)号：US09395804B2
公开(公告)日：2016-07-19
申请号：US13762621
申请日：2013-02-08
CPC分类号： G06F1/3296 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/30083 , G06F9/3836 , G06F9/3844
摘要： A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
摘要翻译： 电路装置为处理单元的分支预测逻辑中的一个或多个功能单元维持功率使用预测信息，使得功能单元的功耗可以在分支指令的执行时与执行分支指令相关联地选择性地减小， 在执行这种分支指令之后，单元将空闲。
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公开(公告)号：US09223753B2
公开(公告)日：2015-12-29
申请号：US13793240
申请日：2013-03-11
CPC分类号： G06F17/10 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30189 , G06F9/3861 , G06F2207/382 , G06F2207/3828
摘要： A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value.
摘要翻译： 浮点执行单元能够选择性地重新排列浮点值中的有效位的子集，以用作附加指数位以动态地提供用于浮点计算的扩展范围。 浮点操作数的有效位域可以被认为包括第一和第二部分，其中第一部分能够与第二部分连接以表示浮点值的有效位数，或者提供扩展的范围，被连接 与浮点运算数的指数字段表示浮点值的指数。
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