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公开(公告)号：US11301254B2
公开(公告)日：2022-04-12
申请号：US16521833
申请日：2019-07-25
摘要： A method, system, and/or processor for processing data is disclosed that includes processing a parent stream, detecting a branch instruction in the parent stream, activating an additional child stream, copying the content of a parent mapper copy of the parent stream to an additional child mapper copy, dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, a first parent mapper copy is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream. The method in an aspect includes processing one or more streams and/or one or more threads of execution on one or more execution slices.
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公开(公告)号：US11188340B2
公开(公告)日：2021-11-30
申请号：US16226729
申请日：2018-12-20
发明人： Brian W. Thompto , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/38
摘要： Techniques for parallel execution of instructions in an instruction set are described. The techniques include determining a plurality of instruction streams and paths for a branch in an instruction set and executing the determined paths in parallel such that a mis-predicted path does not cause significant mis-prediction penalties.
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公开(公告)号：US10996995B2
公开(公告)日：2021-05-04
申请号：US16360920
申请日：2019-03-21
发明人： Steven J. Battle , Dung Q. Nguyen , Hung Q. Le , James W. Bishop , Brian W. Thompto , Susan E. Eisen
摘要： A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.
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公开(公告)号：US20210072993A1
公开(公告)日：2021-03-11
申请号：US16563091
申请日：2019-09-06
发明人： Steven J. Battle , Maarten J. Boersma , Niels Fricke , Hung Q. Le , Dung Q. Nguyen , Brian W. Thompto
IPC分类号： G06F9/30
摘要： A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.
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公开(公告)号：US20210026642A1
公开(公告)日：2021-01-28
申请号：US16521833
申请日：2019-07-25
摘要： A method, system, and/or processor for processing data is disclosed that includes processing a parent stream, detecting a branch instruction in the parent stream, activating an additional child stream, copying the content of a parent mapper copy of the parent stream to an additional child mapper copy, dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, a first parent mapper copy is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream. The method in an aspect includes processing one or more streams and/or one or more threads of execution on one or more execution slices.
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公开(公告)号：US20200326978A1
公开(公告)日：2020-10-15
申请号：US16383775
申请日：2019-04-15
发明人： Brian D. Barrick , Steven J. Battle , Joshua W. Bowman , Cliff Kucharski , Hung Q. Le , Dung Q. Nguyen , David R. Terry
摘要： A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.
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公开(公告)号：US20200249946A1
公开(公告)日：2020-08-06
申请号：US16268688
申请日：2019-02-06
发明人： Kenneth L. Ward , Hung Q. Le , Dung Q. Nguyen , Bryan Lloyd
摘要： A computer system, processor, and method for processing information is disclosed that includes determining whether an instruction is a designated instruction, determining whether an instruction following the designated instruction is a subsequent store instruction, speculatively releasing the subsequent store instruction while the designated instruction is pending and before the subsequent store instruction is complete. Preferably, in response to determining that an instruction is the designated instruction, initiating or advancing a speculative tail pointer in an instruction completion table (ICT) to look through the instructions in the ICT following the designated instruction.
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8.发明授权公开(公告)号：US10691459B2
公开(公告)日：2020-06-23
申请号：US15795945
申请日：2017-10-27
IPC分类号： G06F9/30
摘要： Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
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公开(公告)号：US10664275B2
公开(公告)日：2020-05-26
申请号：US16117058
申请日：2018-08-30
发明人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.
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公开(公告)号：US10545762B2
公开(公告)日：2020-01-28
申请号：US15805267
申请日：2017-11-07
发明人： Sam G. Chu , Markus Kaltenbach , Hung Q. Le , Jentje Leenstra , Jose E. Moreira , Dung Q. Nguyen , Brian W. Thompto
摘要： Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.
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