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公开(公告)号：US11868275B2
公开(公告)日：2024-01-09
申请号：US17356752
申请日：2021-06-24
发明人： Manoj Kumar , Gianfranco Bilardi , Kattamuri Ekanadham , Jose E. Moreira , Pratap C. Pattnaik , Jessica Hui-Chun Tseng
CPC分类号： G06F12/1408 , H04L9/0618 , G06F2212/1052
摘要： Aspects of the present disclosure relate to encrypted data processing (EDAP). A processor includes a register file configured to store ciphertext data, an instruction fetch and decode unit configured to fetch and decode instructions, and a functional unit configured to process the stored ciphertext data. The functional unit further includes a decryption module configured to decrypt ciphertext data from the register file to receive cleartext data using an encryption key stored within the functional unit. The functional unit further includes a local buffer configured to store the cleartext data. The functional unit further includes an arithmetic logical unit configured to generate cleartext computation results using the cleartext data The functional unit further includes an encryption module configured to encrypt the cleartext computation results to generate ciphertext computation results for storage back into the register file.
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公开(公告)号：US10936320B1
公开(公告)日：2021-03-02
申请号：US16543540
申请日：2019-08-17
发明人： Kattamuri Ekanadham , Manoj Kumar , Jose E. Moreira , Pratap C. Pattnaik , Jessica Hui-Chun Tseng
摘要： A processor core and methods for managing the processor core. The processor core comprises of a plurality of lanes, each lane comprising a copy of a register file logically shared across the plurality lanes and a plurality of functional units, at least two of the functional units sharing a common cache and a common control unit, where the common control unit concurrently dispatches multiple consecutive instances of an instruction corresponding to multiple successive instances of an inner loop to the plurality of functional units of at least a proper subset of the plurality of lanes; and one or more registers of each copy of the register file, each register being configurable to write a data result from at least one of the functional units to a register in a lane-local mode, a lane-forward mode, and a normal mode.
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公开(公告)号：US10219556B2
公开(公告)日：2019-03-05
申请号：US14966540
申请日：2015-12-11
发明人： David M Daly , David Joel Edelsohn , Kaoutar El Maghraoui , Jose Eduardo Moreira , Priya A Nagpurkar , Jessica Hui-Chun Tseng
IPC分类号： A41D13/00 , A41D31/00 , A41D13/002 , A61B5/00 , A61B5/0205 , A61B5/024 , A61B5/11
摘要： A method includes embedding clothing with at least one sensor and at least one control unit; a power unit powering on the at least one sensor and the at least one control unit; the at least one sensor monitoring a sensed condition; the at least one control unit conducting a heat prediction based on the sensed condition; and the at least one control unit controlling threads within the clothing based on the heat prediction to actively adjust properties of the clothing.
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公开(公告)号：US12008150B2
公开(公告)日：2024-06-11
申请号：US17356784
申请日：2021-06-24
发明人： Jessica Hui-Chun Tseng , Jose E. Moreira , Pratap C. Pattnaik , Manoj Kumar , Kattamuri Ekanadham , Gianfranco Bilardi
CPC分类号： G06F21/79 , G06F21/54 , G06F21/602 , G06F21/74 , G06F21/107
摘要： Aspects of the present disclosure relate to encrypted data processing (EDAP). Encrypted data from a cache to be loaded into a register file can be accessed. The encrypted data can be decrypted to receive cleartext data. The cleartext data can be written to the register file. The cleartext data can be processed using at least one functional unit to receive cleartext computation results. The cleartext computation results can then be written back to the register file.
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公开(公告)号：US20220414023A1
公开(公告)日：2022-12-29
申请号：US17356752
申请日：2021-06-24
发明人： Manoj Kumar , Gianfranco Bilardi , Kattamuri Ekanadham , Jose E. Moreira , Pratap C. Pattnaik , Jessica Hui-Chun Tseng
摘要： Aspects of the present disclosure relate to encrypted data processing (EDAP). A processor includes a register file configured to store ciphertext data, an instruction fetch and decode unit configured to fetch and decode instructions, and a functional unit configured to process the stored ciphertext data. The functional unit further includes a decryption module configured to decrypt ciphertext data from the register file to receive cleartext data using an encryption key stored within the functional unit. The functional unit further includes a local buffer configured to store the cleartext data. The functional unit further includes an arithmetic logical unit configured to generate cleartext computation results using the cleartext data The functional unit further includes an encryption module configured to encrypt the cleartext computation results to generate ciphertext computation results for storage back into the register file.
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公开(公告)号：US10956167B2
公开(公告)日：2021-03-23
申请号：US16434134
申请日：2019-06-06
发明人： Jessica Hui-Chun Tseng , Manoj Kumar , Kattamuri Ekanadham , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/38 , G06F12/0815 , G06F9/30
摘要： An instruction fusion system in which instructions are tagged with extra bits to specify the conditions by which the instructions can be fused is provided. A computing device receives a first instruction to be executed at a processor. The computing device receives a first fusion tag that corresponds to the first instruction, the first fusion tag specifying a condition for fusing the first instruction with another instruction. The computing device determines whether the first instruction is allowed to fuse with a second instruction based on the first fusion tag. When the first instruction is allowed to fuse with the second instruction, the computing device generates a fused instruction based on the first instruction and the second instruction. The computing device executes the fused instruction at the processor.
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公开(公告)号：US20210049016A1
公开(公告)日：2021-02-18
申请号：US16543540
申请日：2019-08-17
发明人： Kattamuri Ekanadham , Manoj Kumar , Jose E. Moreira , Pratap C. Pattnaik , Jessica Hui-Chun Tseng
摘要： A processor core and methods for managing the processor core. The processor core comprises of a plurality of lanes, each lane comprising a copy of a register file logically shared across the plurality lanes and a plurality of functional units, at least two of the functional units sharing a common cache and a common control unit, where the common control unit concurrently dispatches multiple consecutive instances of an instruction corresponding to multiple successive instances of an inner loop to the plurality of functional units of at least a proper subset of the plurality of lanes; and one or more registers of each copy of the register file, each register being configurable to write a data result from at least one of the functional units to a register in a lane-local mode, a lane-forward mode, and a normal mode.
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公开(公告)号：US11900116B1
公开(公告)日：2024-02-13
申请号：US17489746
申请日：2021-09-29
发明人： Dung Q. Nguyen , Brian W. Thompto , Jose E. Moreira , Jessica Hui-Chun Tseng , Pratap C. Pattnaik , Kattamuri Ekanadham , Manoj Kumar
CPC分类号： G06F9/30145 , G06F9/30036 , G06F9/30109 , G06F9/3836 , G06F9/3869
摘要： A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.
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公开(公告)号：US20220414270A1
公开(公告)日：2022-12-29
申请号：US17356784
申请日：2021-06-24
发明人： Jessica Hui-Chun Tseng , Jose E. Moreira , Pratap C. Pattnaik , Manoj Kumar , Kattamuri Ekanadham , Gianfranco Bilardi
摘要： Aspects of the present disclosure relate to encrypted data processing (EDAP). Encrypted data from a cache to be loaded into a register file can be accessed. The encrypted data can be decrypted to receive cleartext data. The cleartext data can be written to the register file. The cleartext data can be processed using at least one functional unit to receive cleartext computation results. The cleartext computation results can then be written back to the register file.
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公开(公告)号：US11294685B2
公开(公告)日：2022-04-05
申请号：US16431723
申请日：2019-06-04
发明人： Jessica Hui-Chun Tseng , Manoj Kumar , Kattamuri Ekanadham , Jose E. Moreira , Pratap C. Pattnaik
摘要： Method and systems for creating a sequence of fused instructions. An instruction stream is obtained, and a window of instructions from the instruction stream is examined and one or more groups of instructions that satisfy one or more fusion rules are identified. One or more of the groups of instructions that satisfy the one or more fusion rules are fused and a maximal length data dependence chain in the instruction stream is analyzed by analyzing every node in a dependence graph in a selected window of instructions. Fusion of an instruction group is prevented based on the maximal length data dependence chain.
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