SECURE IDENTIFICATION OF WAFER AND CHIP

    公开(公告)号:US20230094707A1

    公开(公告)日:2023-03-30

    申请号:US17485999

    申请日:2021-09-27

    IPC分类号: G06F21/73

    摘要: Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.

    Wafer backside engineering for wafer stress control

    公开(公告)号:US11569134B2

    公开(公告)日:2023-01-31

    申请号:US16847811

    申请日:2020-04-14

    摘要: A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.