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1.发明申请Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device 失效在DRAM器件的位线接触的氮化物衬垫层的反应离子蚀刻期间减少氮化物栅极帽层的侵蚀的方法公开(公告)号：US20040195607A1
公开(公告)日：2004-10-07
申请号：US10406645
申请日：2003-04-03
发明人： Michael Maldei , Prakash C. Dev , David Dobuzinsky , Johnathan Faltermeier , Thomas S. Rupp , Chienfan Yu , Rajesh Rengarajan , John Benedict , Munir-ud-Din Naeem
IPC分类号： H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119
CPC分类号： H01L27/10888 , H01L21/31116 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.
摘要翻译： 相对于氮化物盖层的蚀刻速率，氮化物衬垫层的蚀刻速率得到改善。 氮化物衬垫层位于衬底附近的位于衬底顶部的堆叠结构的暴露部分。 氮化物覆盖层位于堆叠结构的顶部。 沿堆叠结构的侧壁形成氧化物间隔物。 氮化物衬里层被图案化和蚀刻以在衬底中形成至少一个开口，而氮化物覆盖层基本保持不变。
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公开(公告)号：US20030001200A1
公开(公告)日：2003-01-02
申请号：US09896741
申请日：2001-06-29
IPC分类号： H01L021/336 , H01L029/76 , H01L029/94
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891
摘要： The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.
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