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    High performance CMOS device structure with mid-gap metal gate
    1.
    发明申请
    High performance CMOS device structure with mid-gap metal gate 失效
    高性能CMOS器件结构，具有中间间隙金属栅极

    公开(公告)号：US20030197230A1

    公开(公告)日：2003-10-23

    申请号：US10127196

    申请日：2002-04-19

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (null500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

    Abstract translation: 公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如 需要具有中间间隙金属栅极的CMOS器件。 本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间） ）以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。 对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

    High performance CMOS device structure with mid-gap metal gate
    2.
    发明申请
    High performance CMOS device structure with mid-gap metal gate 失效

    公开(公告)号：US20040171205A1

    公开(公告)日：2004-09-02

    申请号：US10795672

    申请日：2004-03-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    IPC: H01L021/8238

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (null500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

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