公开(公告)号：US20200167163A1

公开(公告)日：2020-05-28

申请号：US16200191

申请日：2018-11-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sheldon Levenstein ,  Brian W. Thompto ,  David S. Levitan

IPC分类号： G06F9/38

摘要： A processor reads at least one instruction comprising at least one of a branch instruction and a non-branch instruction. In response to the branch instruction comprising a conditional branch instruction and set in dynamic mode, the processor dynamically predicts a branch path as taken or not taken. The processor, in response to the instruction fetch unit set in static mode for a conditional branch instruction and static branch prediction setting bits received with the conditional branch instruction specifying static branch prediction, statically sets the branch path as taken or not taken according to the static branch prediction setting bits received with the branch instruction. The processor selectively sets the operation of the processor temporarily from the dynamic mode to the static mode only in response to detecting a type of the at least one instruction matches a type of instruction qualifying to trigger static branch prediction.

公开(公告)号：US20180151248A1

公开(公告)日：2018-05-31

申请号：US15898893

申请日：2018-02-19

申请人： International Business Machines Corporation

发明人： Harry Barowski ,  Sheldon Levenstein ,  Pradip Patel ,  Daniel Rodko ,  Gordon B. Sapp ,  Rolf Sautter

IPC分类号： G11C29/40 ,  G11C29/44

CPC分类号： G11C29/40 ,  G11C15/00 ,  G11C29/024 ,  G11C29/14 ,  G11C29/44 ,  G11C2029/3602

摘要： The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

公开(公告)号：US10170199B2

公开(公告)日：2019-01-01

申请号：US15898893

申请日：2018-02-19

申请人： International Business Machines Corporation

发明人： Harry Barowski ,  Sheldon Levenstein ,  Pradip Patel ,  Daniel Rodko ,  Gordon B. Sapp ,  Rolf Sautter

IPC分类号： G11C29/40 ,  G11C29/44 ,  G11C15/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/36

摘要： The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

公开(公告)号：US11163577B2

公开(公告)日：2021-11-02

申请号：US16200191

申请日：2018-11-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sheldon Levenstein ,  Brian W. Thompto ,  David S. Levitan

IPC分类号： G06F9/30 ,  G06F9/38

摘要： A processor reads at least one instruction comprising at least one of a branch instruction and a non-branch instruction. In response to the branch instruction comprising a conditional branch instruction and set in dynamic mode, the processor dynamically predicts a branch path as taken or not taken. The processor, in response to the instruction fetch unit set in static mode for a conditional branch instruction and static branch prediction setting bits received with the conditional branch instruction specifying static branch prediction, statically sets the branch path as taken or not taken according to the static branch prediction setting bits received with the branch instruction. The processor selectively sets the operation of the processor temporarily from the dynamic mode to the static mode only in response to detecting a type of the at least one instruction matches a type of instruction qualifying to trigger static branch prediction.

公开(公告)号：US10528352B2

公开(公告)日：2020-01-07

申请号：US15064024

申请日：2016-03-08

申请人： International Business Machines Corporation

发明人： Bryan G. Hickerson ,  Sheldon Levenstein ,  David S. Levitan ,  Albert J. Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875

摘要： Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.

公开(公告)号：US10175987B2

公开(公告)日：2019-01-08

申请号：US15072717

申请日：2016-03-17

申请人： International Business Machines Corporation

发明人： Richard J. Eickemeyer ,  Sheldon Levenstein ,  David S. Levitan ,  Mauricio J. Serrano

IPC分类号： G06F9/38 ,  G06F9/32 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/0862 ,  G06F9/30

摘要： Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

公开(公告)号：US20180174666A1

公开(公告)日：2018-06-21

申请号：US15898861

申请日：2018-02-19

申请人： International Business Machines Corporation

发明人： Harry Barowski ,  Sheldon Levenstein ,  Pradip Patel ,  Daniel Rodko ,  Gordon B. Sapp ,  Rolf Sautter

IPC分类号： G11C29/40 ,  G11C29/44

CPC分类号： G11C29/40 ,  G11C15/00 ,  G11C29/024 ,  G11C29/14 ,  G11C29/44 ,  G11C2029/3602

摘要： The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

公开(公告)号：US10664279B2

公开(公告)日：2020-05-26

申请号：US16239766

申请日：2019-01-04

申请人： International Business Machines Corporation

发明人： Richard J. Eickemeyer ,  Sheldon Levenstein ,  David S. Levitan ,  Mauricio J. Serrano

IPC分类号： G06F9/38 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/0862

摘要： Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

公开(公告)号：US10593420B2

公开(公告)日：2020-03-17

申请号：US15898861

申请日：2018-02-19

申请人： International Business Machines Corporation

发明人： Harry Barowski ,  Sheldon Levenstein ,  Pradip Patel ,  Daniel Rodko ,  Gordon B. Sapp ,  Rolf Sautter

IPC分类号： G11C29/40 ,  G11C29/44 ,  G11C15/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/36

摘要： The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

公开(公告)号：US10079070B2

公开(公告)日：2018-09-18

申请号：US15298360

申请日：2016-10-20

申请人： International Business Machines Corporation

发明人： Harry Barowski ,  Sheldon Levenstein ,  Pradip Patel ,  Daniel Rodko ,  Gordon B. Sapp ,  Rolf Sautter

IPC分类号： G11C29/40 ,  G11C29/44

CPC分类号： G11C29/40 ,  G11C15/00 ,  G11C29/024 ,  G11C29/14 ,  G11C29/44 ,  G11C2029/3602

摘要： The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.