公开(公告)号：US20190095550A1

公开(公告)日：2019-03-28

申请号：US15714086

申请日：2017-09-25

申请人： International Business Machines Corporation

发明人： Dureseti Chidambarrao ,  Jason D. Hibbeler ,  Dongbing Shao ,  Steven Zebertavage

IPC分类号： G06F17/50

摘要： A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

公开(公告)号：US10592627B2

公开(公告)日：2020-03-17

申请号：US15816210

申请日：2017-11-17

申请人： International Business Machines Corporation

发明人： Dureseti Chidambarrao ,  Jason D. Hibbeler ,  Dongbing Shao ,  Steven Zebertavage

IPC分类号： G06F17/50 ,  H01L27/02

摘要： A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

公开(公告)号：US20190095551A1

公开(公告)日：2019-03-28

申请号：US15816210

申请日：2017-11-17

申请人： International Business Machines Corporation

发明人： Dureseti Chidambarrao ,  Jason D. Hibbeler ,  Dongbing Shao ,  Steven Zebertavage

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/10 ,  G06F2217/12 ,  H01L27/0207

摘要： A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.