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1.发明申请Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution 有权用于宽带宽共振全局时钟分配的可调谐扇区缓冲区公开(公告)号：US20140223210A1
公开(公告)日：2014-08-07
申请号：US13759646
申请日：2013-02-05
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G.R. Thomson
CPC分类号： G06F1/10 , G06F1/324 , Y02D10/126
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
摘要翻译： 宽带谐振时钟分布包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格和被配置为接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器。 可调谐扇区缓冲器被配置为基于所识别的谐振或非谐振模式来设置时钟信号的延迟和转换速率。
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公开(公告)号：US20140167832A1
公开(公告)日：2014-06-19
申请号：US13719408
申请日：2012-12-19
发明人： Thomas J. Bucelot , Alan Drake , Joshua D. Friedrich , Jason D. Hibbeler , Liang-Teck Pang , William R. Reohr , Phillip John Restle , Gregory S. Still , Michael G.R. Thomson
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.
摘要翻译： 描述了具有能够从非共振时钟模式转换到第一谐振时钟模式的时钟分配网络的集成电路。在一系列时钟周期内，逐渐完成在时钟模式之间或各种谐振时钟频率之间的转换。 例如，当从非共振时钟模式转换到第一谐振时钟模式时，时钟扇区驱动器的强度在一系列时钟周期内减小，并且与谐振电路相关联的多个谐振开关中的各个谐振开关被修改 协调减少时钟扇区驱动程序的实力。
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公开(公告)号：US09612612B2
公开(公告)日：2017-04-04
申请号：US14706166
申请日：2015-05-07
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
CPC分类号： G06F1/10 , G06F1/324 , Y02D10/126
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
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公开(公告)号：US20160329317A1
公开(公告)日：2016-11-10
申请号：US15098406
申请日：2016-04-14
CPC分类号： H01L27/0251 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L29/0657 , Y02P90/265
摘要： Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.
摘要翻译： 提供了使用天线规则来检查集成电路的设计的方法。 一种方法包括基于晶体管的分流路径的电阻相对于天线的尺寸和晶体管的尺寸来确定晶体管的品质因数。 该方法还包括将确定的品质因数与极限进行比较。 该方法还包括当品质因数小于极限时，认为晶体管通过天线规则，并且当品质因数大于极限时，认为晶体管失效天线规则。 确定和比较由计算机设备执行。
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5.发明授权Setting switch size and transition pattern in a resonant clock distribution system 有权在谐振时钟分配系统中设置开关尺寸和转换模式公开(公告)号：US09268886B2
公开(公告)日：2016-02-23
申请号：US14136651
申请日：2013-12-20
CPC分类号： G06F17/5009 , G06F17/5045 , G06F17/5068 , G06F2217/62 , G06F2217/78 , H03K5/00 , H03K2005/00195
摘要： Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
摘要翻译： 提供了时钟分配网络中的回收能量。 一种方法包括创建包括时钟网格的谐振时钟电路。 该方法还包括提供分布在时钟网格中的谐振结构。 该方法还包括提供控制谐振结构以在非谐振模式和谐振模式之间切换的开关。 该方法还包括确定通过迭代地增加开关的尺寸来最小化谐振时钟电路的功耗的开关尺寸，并且对于每个迭代增加的尺寸，确定谐振时钟电路消耗的功率。
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公开(公告)号：US09054682B2
公开(公告)日：2015-06-09
申请号：US13759311
申请日：2013-02-05
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译： 宽带谐振时钟分配包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格，配置成接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器，至少一个电感器， 至少一个可调谐电阻开关和电容器网络。 可调谐扇区缓冲器可编程设置时钟信号的延时和转换速率。 电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。 所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。
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7.发明授权Variable resistance switch for wide bandwidth resonant global clock distribution 有权用于宽带宽谐振全局时钟分配的可变电阻开关公开(公告)号：US08704576B1
公开(公告)日：2014-04-22
申请号：US13759697
申请日：2013-02-05
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译： 宽带谐振时钟分布包括被配置为将时钟信号分配到集成电路的多个部件，至少一个电感器，至少一个可调电阻开关和电容器网络的时钟网格。 电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。 所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。
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公开(公告)号：US09741707B2
公开(公告)日：2017-08-22
申请号：US15098406
申请日：2016-04-14
CPC分类号： H01L27/0251 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L29/0657 , Y02P90/265
摘要： Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.
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公开(公告)号：US20160328513A1
公开(公告)日：2016-11-10
申请号：US15098396
申请日：2016-04-14
IPC分类号： G06F17/50
CPC分类号： H01L27/0251 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L29/0657 , Y02P90/265
摘要： Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.
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公开(公告)号：US09378329B1
公开(公告)日：2016-06-28
申请号：US14707576
申请日：2015-05-08
IPC分类号： G06F17/50 , H01L23/535 , H01L29/78
CPC分类号： H01L27/0251 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L29/0657 , Y02P90/265
摘要： Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.
摘要翻译： 提供了使用天线规则来检查集成电路的设计的方法。 一种方法包括基于晶体管的分流路径的电阻相对于天线的尺寸和晶体管的尺寸来确定晶体管的品质因数。 该方法还包括将确定的品质因数与极限进行比较。 该方法还包括当品质因数小于极限时，认为晶体管通过天线规则，并且当品质因数大于极限时，认为晶体管失效天线规则。 确定和比较由计算机设备执行。
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