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公开(公告)号：US20200184024A1
公开(公告)日：2020-06-11
申请号：US16678835
申请日：2019-11-08
Applicant: IonQ, Inc. , Duke University
Inventor： Yunseong NAM , Dmitri MASLOV , Jungsang KIM , Ken BROWN
Abstract: The disclosure describes a method, an apparatus, a computer-readable medium, and/or means for reducing two-qubit gates in quantum circuits may include receiving a netlist including information relating to a first plurality of two-qubit quantum gates that form the quantum circuits, performing a controlled gate cancellation operation on the information relating to a first plurality of two-qubit quantum gates to produce a second plurality of two-qubit quantum gates that is functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is larger than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates, generating a new netlist containing information about the second plurality of two-qubit quantum gates, and providing the new netlist to implement a functionality of the quantum circuits based on the second plurality of two-qubit quantum gates.
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公开(公告)号：US20220083889A1
公开(公告)日：2022-03-17
申请号：US17448652
申请日：2021-09-23
Applicant: University of Maryland, College Park , IonQ, Inc.
Inventor： Caroline FIGGATT , Aaron OSTRANDER , Norbert M. LINKE , Kevin A. LANDSMAN , Daiwei ZHU , Dmitri MASLOV , Christopher MONROE
Abstract: The disclosure describes various aspects related to enabling effective multi-qubit operations, and more specifically, to techniques for enabling parallel multi-qubit operations on a universal ion trap quantum computer. In an aspect, a method of performing quantum operations in an ion trap quantum computer or trapped-ion quantum system includes implementing at least two parallel gates of a quantum circuit, each of the at least two parallel gates is a multi-qubit gate, each of the at least two parallel gates is implemented using a different set of ions of a plurality of ions in a ion trap, and the plurality of ions includes four or more ions. The method further includes simultaneously performing operations on the at least two parallel gates as part of the quantum operations. A trapped-ion quantum system and a computer-readable storage medium corresponding to the method described above are also disclosed.
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公开(公告)号：US20210192113A1
公开(公告)日：2021-06-24
申请号：US17165707
申请日：2021-02-02
Applicant: UNIVERSITY OF MARYLAND, COLLEGE PARK , IonQ, Inc.
Inventor： Yunseong NAM , Dmitri MASLOV , Andrew CHILDS , Neil Julien ROSS , Yuan SU
IPC: G06F30/327 , G06F30/39 , G06N10/00
Abstract: The disclosure describes the implementation of automated techniques for optimizing quantum circuits of the size and type expected in quantum computations that outperform classical computers. The disclosure shows how to handle continuous gate parameters and report a collection of fast algorithms capable of optimizing large-scale-scale quantum circuits. For the suite of benchmarks considered, the techniques described obtain substantial reductions in gate counts. In particular, the techniques in this disclosure provide better optimization in significantly less time than previous approaches, while making minimal structural changes so as to preserve the basic layout of the underlying quantum algorithms. The results provided by these techniques help bridge the gap between computations that can be run on existing quantum computing hardware and more advanced computations that are more challenging to implement in quantum computing hardware but are the ones that are expected to outperform what can be achieved with classical computers.
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Patent Agency Ranking
公开(公告)号：US20190121921A1
公开(公告)日：2019-04-25
申请号：US16164586
申请日：2018-10-18
Applicant: University of Maryland, College Park , IonQ Inc.
Inventor： Yunseong NAM , Dmitri MASLOV , Andrew CHILDS , Neil Julien ROSS , Yuan SU
Abstract: The disclosure describes the implementation of automated techniques for optimizing quantum circuits of the size and type expected in quantum computations that outperform classical computers. The disclosure shows how to handle continuous gate parameters and report a collection of fast algorithms capable of optimizing large-scale-scale quantum circuits. For the suite of benchmarks considered, the techniques described obtain substantial reductions in gate counts. In particular, the techniques in this disclosure provide better optimization in significantly less time than previous approaches, while making minimal structural changes so as to preserve the basic layout of the underlying quantum algorithms. The results provided by these techniques help bridge the gap between computations that can be run on existing quantum computing hardware and more advanced computations that are more challenging to implement in quantum computing hardware but are the ones that are expected to outperform what can be achieved with classical computers.
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5.发明公开公开(公告)号：US20240249040A1
公开(公告)日：2024-07-25
申请号：US18483261
申请日：2023-10-09
Applicant: IonQ, Inc.
Inventor： Yunseong NAM , Dmitri MASLOV
CPC classification number: G06F30/20 , G06F11/004 , G06N10/00 , G06N10/60 , G06N10/40
Abstract: The disclosure describes various aspects of techniques for optimal fault-tolerant implementations of controlled-Zα gates and Heisenberg interactions. Improvements in the implementation of the controlled-Zα gate can be made by using a clean ancilla and in-circuit measurement. Various examples are described that depend on whether the implementation is with or without measurement and feedforward. The implementation of the Heisenberg interaction can leverage the improved controlled-Zα gate implementation. These implementations can cut down significantly the implementation costs associated with fault-tolerant quantum computing systems.
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公开(公告)号：US20230368056A1
公开(公告)日：2023-11-16
申请号：US18309486
申请日：2023-04-28
Applicant: University of Maryland, College Park , IonQ, Inc.
Inventor： Caroline FIGGATT , Aaron OSTRANDER , Norbert M. LINKE , Kevin A. LANDSMAN , Daiwei ZHU , Dmitri MASLOV , Christopher MONROE
Abstract: The disclosure describes various aspects related to enabling effective multi-qubit operations, and more specifically, to techniques for enabling parallel multi-qubit operations on a universal ion trap quantum computer. In an aspect, a method of performing quantum operations in an ion trap quantum computer or trapped-ion quantum system includes implementing at least two parallel gates of a quantum circuit, each of the at least two parallel gates is a multi-qubit gate, each of the at least two parallel gates is implemented using a different set of ions of a plurality of ions in a ion trap, and the plurality of ions includes four or more ions. The method further includes simultaneously performing operations on the at least two parallel gates as part of the quantum operations. A trapped-ion quantum system and a computer-readable storage medium corresponding to the method described above are also disclosed.
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7.发明申请公开(公告)号：US20190258757A1
公开(公告)日：2019-08-22
申请号：US16275030
申请日：2019-02-13
Applicant: IonQ, Inc.
Inventor： Yunseong NAM , Dmitri MASLOV
Abstract: The disclosure describes various aspects of techniques for optimal fault-tolerant implementations of controlled-Za gates and Heisenberg interactions. Improvements in the implementation of the controlled-Za gate can be made by using a clean ancilla and in-circuit measurement. Various examples are described that depend on whether the implementation is with or without measurement and feedforward. The implementation of the Heisenberg interaction can leverage the improved controlled-Za gate implementation. These implementations can cut down significantly the implementation costs associated with fault-tolerant quantum computing systems.
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公开(公告)号：US20190205783A1
公开(公告)日：2019-07-04
申请号：US16234112
申请日：2018-12-27
Applicant: University of Maryland, College Park , IonQ, Inc.
Inventor： Yunseong NAM , Dmitri MASLOV
CPC classification number: G06N10/00 , G06F15/8007 , G06F17/14
Abstract: The disclosure describes various aspects of techniques for using global interactions in efficient quantum circuit constructions. More specifically, this disclosure describes ways to use a global entangling operator to efficiently implement circuitry common to a selection of important quantum algorithms. The circuits may be constructed with global Ising entangling gates (e.g., global Mølmer-Sørenson gates or GMS gates) and arbitrary addressable single-qubit gates. Examples of the types of circuits that can be implemented include stabilizer circuits, Toffoli-4 gates, Toffoli-n gates, quantum Fourier transformation (QTF) circuits, and quantum Fourier adder (QFA) circuits. In certain instances, the use of global operations can substantially improve the entangling gate count.
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